Multi-Level Memory Hierarchy Sorting with Dynamic Page Sizing
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Solution Overview
Problem
Existing sorting techniques face inefficiencies when dealing with large datasets that exceed the capacity of internal memory, leading to increased processing time and storage requirements due to disk latency and the need for multi-pass merging.
Innovation Solution
The implementation of a three-level memory hierarchy using RAM, flash memory, and disk drives, optimizing page sizes and data transfer to balance access latency and transfer bandwidth, and employing a multi-phase merge-sort process that minimizes data movement and maximizes bandwidth utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external sorting is used when internal memory capacity is insufficient, then sorting capability is improved, but processing time increases due to disk latency
Solution Approach 1:
The patent divides the sorting process into multiple passes, with each pass handling a portion of the data. Data is segmented into chunks that can be processed in parallel across multiple disk drives, reducing the impact of disk latency by distributing I/O operations across multiple devices simultaneously.
Solution Approach 2:
The patent introduces a multi-dimensional approach by using multiple disk drives in parallel and implementing a hierarchical memory structure with different levels of caching. This adds spatial dimensionality to the sorting process, allowing simultaneous operations across multiple storage devices and reducing overall processing time.
2Manufacturing precision
If multi-pass merging is used to sort large datasets, then sorting completeness is improved, but storage requirements increase
Solution Approach 1:
The patent performs preliminary sorting of data into sorted runs during the first pass, organizing data in advance for efficient merging in subsequent passes. This preliminary organization reduces the storage overhead required during merging operations, as data is already structured for the next phase of processing.
Solution Approach 2:
The patent uses buffering and caching mechanisms that create temporary copies of data in memory during the merging process. These copies allow multiple passes to access the same data without requiring permanent storage of intermediate results, reducing overall storage requirements while maintaining sorting completeness.
3Speed
If data is transferred between multiple memory layers, then access latency is reduced, but transfer bandwidth requirements increase
Solution Approach 1:
The patent implements different page sizes optimized for specific memory layers, with smaller pages for faster memory and larger pages for slower storage. This local optimization allows data to be transferred in the most efficient format for each specific memory layer, reducing overall transfer bandwidth requirements while maintaining low access latency.
Solution Approach 2:
The patent dynamically adjusts transfer parameters such as page size and block size based on the source and destination memory layers. By changing these parameters according to the specific transfer operation, the system optimizes bandwidth utilization and reduces the total amount of data that needs to be transferred across the memory hierarchy.
Data Source
AI summary
A method, executed on a suitably programmed processor, provides for ordering records using a memory hierarchy. The memory hierarchy includes and two or more lower levels of the memory hierarchy. The method includes the steps of (a) receiving unsorted input records; (b) reading the input records in pages and writing one or more pages of the input records to the primary memory; (c) sorting the pages of input records to create a run; (d) if a size of the run exceeds primary memory capacity, moving data that just exceeds the primary memory capacity to a secondary level of the memory hierarchy; (e) repeating steps (a)-(d) until either (i) all unsorted input records have been read into primary memory and sorted, or (ii) a capacity of the secondary level of the memory hierarchy is exceeded; (f) following step (e)(ii), moving data that just exceeds the secondary memory capacity from the secondary level to a tertiary level of the memory hierarchy until the capacity of the secondary level no longer is exceeded; and (g) following either of steps (c), (e)(i), or (f), merging runs to create a merge output.