3D Memory Cell Layout for Hole Alignment and Etch Reliability
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently manufacturing high-quality memory dies due to positional discrepancies between memory holes on different layers, leading to potential defects and reduced quality, and there is a need to utilize previously dead spaces for functional regions without increasing the device area.
Innovation Solution
The semiconductor memory device incorporates a unique layer structure with alternating conducting and insulating layers, and strategically forms memory holes and inspection regions to ensure precise alignment and quality inspection, while also utilizing a discharge region to prevent arcing during etching processes, thereby enhancing manufacturing efficiency and product quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If memory holes are formed on different layers during manufacturing, then memory device functionality is achieved, but positional discrepancies occur leading to reduced manufacturing precision
Solution Approach 1:
The patent introduces an intermediary alignment mark structure that mediates between different memory hole layers. The alignment mark includes a first marker on a first layer and a second marker on a second layer, which serve as reference points to ensure precise positional alignment during the formation of memory holes across multiple layers, thereby preventing positional discrepancies and maintaining manufacturing precision
Solution Approach 2:
The patent implements a feedback mechanism through inspection regions that verify the positional alignment of memory holes after formation. The inspection region includes structures that allow detection of whether memory holes are properly aligned across layers, providing feedback information that can be used to adjust subsequent manufacturing processes and ensure consistent positioning accuracy
2Area of stationary object
If dead spaces are utilized for functional regions, then device area is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent applies multi-functionality by designing the alternating conducting and insulating layers to serve dual purposes: they provide the necessary structural framework for memory hole formation while simultaneously creating usable functional regions within previously dead spaces. The conducting layers can serve as both structural supports and functional conductive paths, and the insulating layers provide both separation and isolation functions, thereby utilizing all space efficiently without increasing overall device area
Solution Approach 2:
The patent segments the device structure into alternating conducting and insulating layers, where each layer type serves specific functions. This segmentation allows dead spaces to be divided and repurposed as functional regions while maintaining clear boundaries and organizational structure, preventing the complexity from becoming unmanageable despite the increased functional density
3Reliability
If discharge regions are added to prevent arcing, then manufacturing reliability is improved, but device area increases
Solution Approach 1:
The patent merges the discharge region functionality with existing structural elements rather than adding separate dedicated discharge regions. The conducting layers and insulating layers are configured to work together as integrated discharge pathways that prevent arcing during etching processes. By combining the discharge function with the alternating layer structure already present in the device, the patent achieves reliable arc prevention without increasing the overall device area
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.