3D Memory Hole Structure for Wide Bottom Diameter Etching
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Solution Overview
Problem
In the manufacturing of semiconductor memory devices, particularly three-dimensional non-volatile memory, the increasing number of stacked insulating layers poses a challenge in forming memory holes with a wide bottom diameter at a high etching rate, as existing etching methods often result in tapered shapes that hinder effective conductivity to the source line.
Innovation Solution
The solution involves forming memory holes with a two-step bowing shape by adjusting the thickness of insulating layers within the stacked body, where multiple insulating layers are made thicker than others at specific height positions, reducing deposition during etching, and using low-temperature plasma etching with fluorocarbon and hydrogen gases to expand the bottom diameter while maintaining a high etching rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form memory holes through stacked insulating layers, then the etching process can be completed, but the memory holes acquire a tapered shape with small bottom diameter, reducing conductivity to the source line
Solution Approach 1:
The patent applies local quality by making specific insulating layers (first and second insulating layers) thicker than others at predetermined height positions within the stacked body. This localized thickness variation creates specific deposition patterns during etching that generate bowing shapes in the memory hole, thereby expanding the bottom diameter at critical regions while maintaining overall etching completion.
2Productivity
If the number of stacked insulating layers is increased to enhance memory structure, then memory capacity improves, but forming memory holes with wide bottom diameter becomes more difficult
Solution Approach 1:
The patent segments the insulating layers into different thickness categories, with specific layers (first and second insulating layers) made thicker than others. This segmentation strategy allows the etching process to generate controlled deposition patterns that create bowing shapes, thereby maintaining wide bottom diameter capability even as the total number of stacked layers increases for enhanced memory capacity.
3Productivity
If etching rate is increased to improve manufacturing efficiency, then productivity improves, but control over memory hole shape deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-configuring the insulating layer structure with specific thicker layers (first and second insulating layers) at predetermined height positions before the etching process begins. This preliminary structural arrangement ensures that during high-speed etching, deposition occurs in controlled patterns that automatically generate the desired bowing shapes, thereby maintaining shape control even at high etching rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively forms memory holes with a large bottom diameter and high etching rate, ensuring efficient conductivity to the source line, thereby enhancing the memory structure's performance and throughput in semiconductor memory devices.
Implementation Method 1
using low-temperature plasma etching with fluorocarbon and hydrogen gases
Implementation Method 2
reducing deposition during etching
Implementation Method 3
reducing deposition during etching
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a lower layer, a stacked body above the lower layer with first conductive layers and first insulating layers alternately stacked. A pillar penetrates through the stacked body to reach the lower layer. At least one first insulating layer other than the lowest among the first insulating layers in a first region of the stacked body is thicker than first insulating layers in a second region above the first region. The pillar has a first bowing shape at the height of the at least one thicker first insulating layer and a second bowing shape at a height in the second region.