Memory Hub Bit-Lane Rerouting for Fault Tolerance
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Solution Overview
Problem
Conventional memory systems with memory hub architecture face limitations in communication bandwidth due to the relatively low speed of memory controllers and devices, and they lack effective redundancy to maintain operation when multiple bit-lanes become defective.
Innovation Solution
A memory hub architecture with a switch and switching circuit that reroutes bit-lane connections between memory modules, allowing for continued operation even when multiple bit-lanes fail, by coupling bit-lane terminals between memory hubs and memory devices through a flexible re-routing mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple memory modules are coupled through a memory controller to increase bandwidth, then communication bandwidth is improved, but the system becomes vulnerable to bit-lane failures that can disable entire communication paths
Solution Approach 1:
The bit-lane interface is segmented into multiple independent sub-lanes within each memory hub. When a failure occurs, only the affected sub-lane is disabled while other sub-lanes remain operational, allowing partial functionality to be maintained rather than complete system failure.
Solution Approach 2:
The memory hub incorporates dynamic reconfiguration capability through switching circuitry that can reallocate bit-lane connections in real-time. When a bit-lane failure is detected, the system dynamically reroutes signals through alternative paths, adapting the communication topology to maintain operation.
2Speed
If dedicated bit-lanes are assigned to specific memory devices for high-speed communication, then communication speed is improved, but the system lacks flexibility to handle bit-lane failures
Solution Approach 1:
Each bit-lane terminal in the memory hub is designed to be multi-functional, capable of connecting to multiple different memory devices or controllers depending on configuration needs. This universal connectivity allows the same physical lane to serve different logical purposes based on system requirements and failure conditions.
Solution Approach 2:
The memory hub acts as an intermediary layer between memory devices and controllers, providing switching circuitry that can mediate connections between any device and any controller. This intermediate switching capability enables flexible rerouting around failures while maintaining high-speed communication through the hub's centralized control.
3Reliability
If a switch with multiple paths is implemented in the memory hub, then redundancy against bit-lane failures is improved, but device complexity increases
Solution Approach 1:
The memory hub implements switching capability for only the necessary subset of bit-lanes rather than all possible connections. By providing partial redundancy through selective switching paths for critical bit-lanes while omitting less critical paths, the system achieves adequate fault tolerance with reduced complexity compared to a fully redundant switching fabric.
Data Source
AI summary
A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub controller through any intervening memory modules. The signals are coupled to and from the memory modules through high-speed bit-lanes. In the a bit-lane connected to any of the memory hubs is inoperative, the memory hub re-routes signals that would be coupled through the inoperative bit-lane to an adjacent bit lane. When the signal reaches a memory hub in which the bit-lane is no longer inoperative, the memory hub routes the signal back to the original bit lane. In this manner, multiple bit-lane failures can be accommodated using a signal extra bit-lane.