Memory Hub Data Bypass Circuit for Bi-Directional Bus
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Solution Overview
Problem
Conventional memory systems face limitations in increasing bandwidth and reducing latency due to hardware constraints, and they struggle with data collisions on bi-directional memory buses, which hinder efficient data transfer and lead to increased costs and complexity.
Innovation Solution
A memory hub with a data bypass circuit that temporarily stores write data, allowing read data to pass through while write data is stored, thereby preventing data collisions and enabling earlier sequencing of write commands without waiting for read data to complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory data bus speed is increased to improve bandwidth, then data transfer rate is improved, but data collisions occur on the bi-directional bus and signal integrity deteriorates
Solution Approach 1:
The patent segments the bi-directional data bus into separate read and write paths by introducing a read data register. This segmentation allows read and write operations to occur simultaneously without interfering with each other, thereby maintaining signal integrity while enabling higher bandwidth operation.
Solution Approach 2:
The read data register acts as an intermediary element that temporarily holds read data, allowing the write data path to operate independently. This intermediary structure prevents data collisions on the bi-directional bus while maintaining high-speed data transfer capability.
2Loss of time
If memory data bus speed is increased to reduce latency, then data transfer speed is improved, but latency is not linearly reduced due to hardware limitations
Solution Approach 1:
The patent implements preliminary action by allowing write commands to be scheduled and executed before read operations complete. The read data register enables write data to be latched and transmitted independently of read operation timing, thereby reducing latency without compromising bandwidth.
3Reliability
If additional memory interfaces are added to maintain signal integrity at high speeds, then signal quality is maintained, but system cost and complexity increase
Solution Approach 1:
The read data register serves multiple functions: it buffers read data, enables independent write operations, and maintains signal integrity on the bi-directional bus. This multi-functionality allows the system to achieve high-speed operation with existing interfaces rather than requiring additional memory interfaces.
Data Source
AI summary
A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.