Memory Hub Cache for Failed DRAM Cell Replacement
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Solution Overview
Problem
High-performance computing systems face reliability issues due to memory cell failures in DRAM chips, leading to performance degradation and costly repairs, as failed memory cells can cause errors and require replacement of entire memory blocks.
Innovation Solution
Embedding a cache within a memory hub device that can replace failed memory cells by correcting errors and using the cache for subsequent read/write operations, thereby extending the system's mean-time-before-failure and reducing repair actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory systems are used without cache replacement, then the system structure is simpler, but memory reliability deteriorates due to failed memory cells causing errors and requiring repair actions
Solution Approach 1:
The patent embeds a cache structure within the memory hub device, nesting the cache inside the existing memory module architecture. This allows the cache to serve as a replacement for failed memory cells without requiring external replacement components, thus improving reliability while maintaining relatively compact system structure.
Solution Approach 2:
The cache in the memory hub acts as an intermediary between the memory controller and the physical memory devices. When memory cells fail, the cache provides alternative storage locations for the affected data, mediating the failure and preventing system errors without requiring direct intervention or system shutdown.
2Reliability
If memory cells are replaced with cache locations, then memory reliability improves, but the device complexity increases due to additional cache management operations
Solution Approach 1:
The memory hub controller automatically manages the cache replacement process without requiring external intervention. When memory errors are detected, the controller autonomously transfers data between memory devices and cache locations, performing self-diagnosis and self-repair operations that maintain system availability while minimizing the need for complex external management mechanisms.
Solution Approach 2:
The system performs preliminary error detection and data validation operations before failures become critical. By checking data integrity and proactively managing cache replacements before memory blocks completely fail, the system reduces the complexity of handling catastrophic failures while maintaining high availability.
3Duration of action of stationary object
If cache is used to replace failed memory cells, then mean-time-before-failure increases, but the loss of time occurs due to additional read/write operations to verify and correct errors
Solution Approach 1:
The system performs error verification operations selectively rather than on every memory access. Cache replacement is triggered only when errors are detected in specific memory locations, performing partial verification actions only where needed. This approach extends mean-time-before-failure while minimizing the time loss associated with error checking and correction operations.
4Reliability
If memory locations are taken out of valid memory space due to failures, then reliability is maintained by avoiding errors, but productivity decreases due to reduced usable memory capacity
Solution Approach 1:
The cache structure serves multiple functions: it acts as both a high-speed buffer for normal memory operations and as a replacement storage for failed memory cell data. This multi-functionality allows the system to maintain data integrity for failed locations while keeping the cache capacity available for productive memory operations, thereby maintaining both reliability and usable memory capacity.
Data Source
AI summary
A mechanism is provided for using a cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a set of memory devices coupled to the memory hub device and a cache integrated in the memory hub device. The memory hub device also comprises an integrated memory hub controller that controls the data that is read or written by the memory device data interface to the cache based on a determination whether one or more memory cells within the set of memory devices has failed.