Memory Subsystem Hybrid Decoding for Multi-Component Error Recovery
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Solution Overview
Problem
Conventional memory sub-systems face limitations in data recovery when multiple memory components fail, as they cannot tolerate high average bit error rates or multiple errors in RAID 5 and RAID 6 configurations without additional redundant data or components.
Innovation Solution
Implementing hybrid iterative error correcting code decoding operations and redundancy error correction decoding operations, which combine error correction code decoding and redundancy error correction decoding, using a threshold condition to iteratively correct and reconstruct data without adding redundant memory components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RAID 5 or RAID 6 configurations are used, then data storage capacity is maintained, but the system cannot tolerate high average bit error rates or multiple memory component failures
Solution Approach 1:
The patent combines error correction code decoding and redundancy error correction decoding into a hybrid iterative decoding operation. The ECC decoder and RAID decoder work together in an iterative manner, where the ECC decoder attempts to correct errors first, and if the threshold condition is met (indicating persistent errors), the RAID decoder provides additional redundancy-based correction. This merging of two decoding approaches enables the system to tolerate higher bit error rates and multiple component failures without adding redundant memory components.
2Reliability
If additional redundant memory components are added to tolerate more errors, then data reliability improves, but system cost and complexity increase
Solution Approach 1:
The patent changes the operational parameters of the existing memory sub-system by implementing a threshold-based iterative decoding mechanism. Instead of adding hardware redundancy, it modifies the decoding process to dynamically adjust between ECC-only mode and hybrid ECC-RAID mode based on the threshold condition. This parameter change enables existing components to operate in a more robust error-correction regime, achieving enhanced reliability without increasing component count.
3Reliability
If hybrid iterative decoding operations are implemented, then more bit errors can be corrected, but decoding processing time increases
Solution Approach 1:
The patent implements partial iterative decoding by introducing a threshold condition that determines when to switch from ECC-only decoding to hybrid ECC-RAID decoding. The threshold condition acts as a stopping criterion that prevents excessive iterative cycles. By only engaging in full hybrid decoding when necessary (when the threshold condition is met), the system achieves enhanced error correction capability while limiting the time penalty to only those cases where additional correction is actually needed.
Data Source
AI summary
Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.