Memory IC Backside Power Delivery for Nanowire Scaling
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in lithographic processes, leading to trade-offs between feature dimension and spacing, and traditional front-side power delivery methods increase power network resistance and energy consumption, complicating high-bandwidth computing.
Innovation Solution
Implementing backside power delivery in integrated circuit structures, which allows for independent synthesis of power and signal lines, reducing power network resistance and energy consumption, and enabling more aggressive scaling and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If front-side power delivery is used, then power can be delivered to devices, but power network resistance and energy consumption increase
Solution Approach 1:
The patent delivers power from the backside of the substrate rather than the front side, utilizing the third dimension (vertical depth) to create separate power and signal pathways. This dimensional change allows power to be delivered through dedicated backside interconnect structures directly to device regions, reducing the horizontal current path length and associated resistance on the front side, thereby lowering energy consumption in the power network.
2Productivity
If feature dimensions are scaled down to increase device density, then more devices can be fabricated on a chip, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent employs three-dimensional device structures (such as FinFETs or nanowire transistors with vertical channels) that extend in the vertical dimension rather than relying solely on horizontal scaling. This allows device density to increase through vertical stacking and multi-layer interconnects, thereby reducing the lithographic resolution requirements for patterning while maintaining high device density on the chip.
3Device complexity
If power and signal lines are synthesized together, then routing is simplified, but power network resistance increases
Solution Approach 1:
The patent segments the power delivery function from signal routing by implementing separate backside power interconnect structures and frontside signal interconnect structures. This segmentation allows each network to be independently optimized - power lines can be designed with wider cross-sections and lower resistance paths on the backside, while signal lines maintain their routing flexibility on the frontside, thereby reducing overall power network resistance without excessive routing complexity.
Data Source
AI summary
Structures having memory with backside power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. One of the metal layers includes an array of uninterrupted signal lines. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a ground metal line.