Memory Module ID Allocation via Daisy-Chained Management Bus

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Solution Overview

Problem

Memory modules comprising multiple memories face challenges in efficiently distinguishing and allocating unique identifiers due to differences in location and wiring length, which affects their independent operation.

Innovation Solution

A memory module configuration and method are introduced, utilizing a management bus to allocate unique identifiers (IDs) to memories before power-up, using a side-band interface to ensure each memory receives a distinct ID through serial connections and ID input/output terminals, enabling efficient operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple memories are connected in series with daisy chain ID terminals, then unique ID allocation is enabled for each memory, but the device complexity increases due to additional ID input and output terminals and wiring

Engineering Contradiction:
ImproveID identification accuracyVSAvoidmemory module structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the ID allocation system into segmented components by providing separate ID input terminals and ID output terminals for each memory device. This segmentation allows each memory to be independently identified through the daisy chain connection while maintaining unique ID assignment, resolving the contradiction between precise ID identification and structural simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism through the management bus that facilitates ID setting information transmission between the baseboard management controller and memory devices. This intermediary channel enables unique ID allocation without requiring complex direct connections between all memory devices, thus reducing overall system complexity while maintaining identification accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If ID setting is performed before power-up using side-band interfaces, then independent operation of memories is enabled, but the manufacturing process complexity increases due to additional setup requirements

Engineering Contradiction:
Improvememory independent operationVSAvoidID allocation setup process
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent implements preliminary action by performing ID setting before power-up through the side-band interface. The baseboard management controller pre-configures unique IDs for each memory device via the management bus, allowing memories to operate independently once powered on. This preliminary configuration enables independent operation while the automated nature of the process reduces manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces manual or post-power-up configuration mechanisms with an automated side-band interface system that operates during the power-up sequence. The management bus-based ID setting mechanism substitutes for complex manual setup procedures, enabling independent memory operation while simplifying the manufacturing process through automated configuration.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If a management bus is added for ID setting information transmission, then unique ID allocation is achieved, but the device complexity and wiring length increase

Engineering Contradiction:
Improvememory identification accuracyVSAvoidwiring length
Core Design Contradiction:
Measurement precisionVSLength of stationary object

Solution Approach 1:

The patent makes the management bus universal by using it for multiple purposes: ID setting information transmission, memory device identification, and system configuration. This multi-functionality allows unique ID allocation without requiring separate dedicated wiring for each function, thereby achieving identification accuracy while minimizing additional wiring length compared to having separate专用 channels.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12613797B2Method for memory ID allocation, memory, memory module, and memory system
Publication Date: 2026.04.28 SK HYNIX INC
  • US12613797B2 patent drawing
  • US12613797B2 patent drawing
  • US12613797B2 patent drawing

AI summary

A memory module may include a management bus and a plurality of memories connected in series and connected to the management bus, each of the plurality of memories including an identification (ID) input terminal and an ID output terminal. Among the plurality of memories, a memory, for which an activation signal is applied to an ID input terminal of the memory, may set an ID for the memory in response to ID setting information transmitted on the management bus.