Selective IDR Reset Control in Memory Setting Data Storage
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Solution Overview
Problem
Existing memory devices face inefficiencies in resetting operations due to long durations and the inability to selectively reset memory chips with errors, particularly when soft errors occur in initialization data (IDR) stored in storage circuits.
Innovation Solution
A memory device with a memory cell array divided into cell blocks, featuring a setting data storage circuit and control logic that allows selective or full resetting of storage regions based on external commands, enabling efficient updating of IDR data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full reset operation is performed on the storage circuit to remove errors in IDR data, then reliability is improved, but the duration of the resetting process increases
Solution Approach 1:
The storage circuit is divided into multiple storage regions, each capable of independent reset control. The control logic selectively resets only the storage regions containing erroneous IDR data rather than performing a full reset of all storage regions, thereby reducing the resetting duration while maintaining reliability.
Solution Approach 2:
Different storage regions are treated differently based on their error status. The control logic identifies and applies reset operations only to specific storage regions with errors, rather than uniformly resetting all regions, optimizing the balance between reliability and duration.
2Reliability
If a full reset operation is performed on all memory chips, then reliability is improved, but productivity decreases
Solution Approach 1:
The erroneous IDR data is extracted and identified in specific storage regions. The control logic then applies reset operations only to these extracted problematic regions rather than resetting all memory chips, improving productivity by eliminating unnecessary reset operations on error-free chips.
Solution Approach 2:
Instead of performing excessive full reset operations on all memory chips, the control logic applies partial reset operations only to the extent necessary - specifically to the storage regions containing errors - thereby maintaining reliability while improving productivity.
3Productivity
If selective reset of individual memory chips is enabled, then productivity is improved, but device complexity increases
Solution Approach 1:
The control logic is designed to handle multiple functions: it can identify errors in IDR data, determine which storage regions need resetting, and execute selective reset operations. This multi-functional approach consolidates what would otherwise require separate control mechanisms, limiting the increase in device complexity.
Solution Approach 2:
The control logic uses feedback from error detection mechanisms to dynamically determine which storage regions require resetting. This feedback-driven approach allows selective reset operation without requiring complex pre-configured control mechanisms, as the system adapts its reset strategy based on actual error conditions.
Data Source
AI summary
A memory device includes a memory cell array having a plurality of cell blocks therein, including at least one cell block configured to store information data read (IDR) data related to setting an operating environment of the memory device. A setting data storage circuit is provided, which includes a plurality of storage regions in which the IDR data, which is read from the at least one cell block, is stored and a reset operation is independently controlled. Control logic is provided, which is configured to control at least one of a reset operation on the setting data storage circuit, and an IDR operation of updating the IDR data to the setting data storage circuit according to a decoding result of an external command. The control logic is configured to selectively reset only some storage regions of the setting data storage circuit in response to a determination that the external command is a first reset command, but reset all storage regions of the setting data storage circuit in response to a determination that the external command is a second reset command.