Memory Output Impedance Calibration Using Averaged Reference Levels
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Solution Overview
Problem
As memory devices operate at higher speeds, signal distortion due to impedance mismatch becomes more pronounced, leading to instability and reduced signal integrity, particularly due to variations in process, voltage, and temperature (PVT).
Innovation Solution
A method and circuit for calibrating the impedance of memory devices by adjusting the output impedance based on an average ZQ code, obtained by comparing power supply and reference voltages, and averaging multiple voltage levels to compensate for voltage drops, thereby stabilizing the driver strength characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If impedance calibration is performed using a single reference voltage level, then the calibration process is simple and fast, but the accuracy of impedance matching deteriorates due to voltage drops during high-speed operation
Solution Approach 1:
The patent performs preliminary actions by storing multiple reference voltage levels (N levels) in advance before calibration. The calibration circuit selects appropriate reference voltage levels from the pre-stored set based on comparison results, enabling accurate compensation for voltage drops without requiring complex real-time adjustments during calibration.
Solution Approach 2:
The patent makes the reference voltage dynamic by selecting different reference voltage levels from a set of N pre-stored levels based on the comparison signal. This dynamic selection allows the calibration circuit to adapt to varying voltage drop conditions during high-speed operation, improving impedance matching accuracy while maintaining a relatively simple calibration structure.
2Reliability
If multiple reference voltage levels are used for calibration, then voltage drop compensation accuracy improves, but the calibration time and process complexity increase
Solution Approach 1:
The patent performs preliminary actions by storing multiple reference voltage levels (N levels) in advance before calibration. The calibration circuit selects appropriate reference voltage levels from the pre-stored set based on comparison results, enabling accurate compensation for voltage drops without requiring complex real-time adjustments during calibration.
Solution Approach 2:
The patent uses partial action by selecting only the necessary number of reference voltage levels from the pre-stored N levels based on the actual voltage drop conditions. This approach avoids using all N levels unnecessarily, thereby reducing calibration time while still achieving sufficient voltage drop compensation accuracy for reliable operation.
3Reliability
If impedance calibration compensates for voltage drops accurately, then driver strength characteristics are maintained, but the calibration circuit complexity increases
Solution Approach 1:
The patent makes the reference voltage dynamic by selecting different reference voltage levels from a set of N pre-stored levels based on the comparison signal. This dynamic selection allows the calibration circuit to adapt to varying voltage drop conditions during high-speed operation, improving impedance matching accuracy while maintaining a relatively simple calibration structure.
Solution Approach 2:
The patent introduces an intermediary element - a set of N pre-stored reference voltage levels that act as intermediaries between the fixed reference voltage source and the varying voltage drop conditions. This intermediary set enables accurate voltage drop compensation without requiring complex real-time voltage generation or adjustment mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves operational stability of memory devices by accurately adjusting impedance to match voltage drops, enhancing signal integrity and reducing driver strength deterioration.
Implementation Method 1
a comparator configured to output a comparison signal by comparing a power supply voltage and a reference voltage
Data Source
AI summary
A method of calibrating impedance of a memory device including a data transmitter includes: outputting a comparison signal by comparing a power supply voltage and a reference voltage, the power supply voltage being supplied to the data transmitter when the data transmitter is driven; storing a voltage level of the reference voltage when the comparison signal changes logical state; adjusting the reference voltage based on the comparison signal such that the voltage level of the reference voltage increases or decreases; and calibrating an output impedance of the memory device based on a digital code corresponding to an average reference voltage level, the average reference voltage level being obtained by averaging a prescribed number of voltage levels of the reference voltage stored as a result of repeatedly outputting the comparison signal, storing the voltage level of the reference voltage, and adjusting the reference voltage.