Semiconductor Memory Impedance Control Circuit
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Solution Overview
Problem
Semiconductor memory devices face challenges with impedance mismatching at interfaces, leading to signal reflection and errors due to varying output resistances of output buffers, which are exacerbated by fast operation speeds and require complex impedance matching circuits.
Innovation Solution
A semiconductor memory device with an impedance-controlling circuit that includes a replica circuit and voltage-generating circuit to control output resistance, allowing for trimming operations to match impedance and reduce errors during testing, enabling efficient testing with reduced hardware and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fast operation speeds are implemented in semiconductor memory devices, then interface speed is improved, but signal reflection and impedance mismatching errors occur
Solution Approach 1:
The patent changes the impedance parameter of the output buffer by selectively connecting different resistance values (e.g., 100Ω, 50Ω, 25Ω) to the output terminal based on the specific application requirements. This allows optimization of signal transmission at high speeds by matching impedance to reduce reflections while maintaining fast operation speeds.
2Reliability
If output resistance is controlled to match impedance, then signal reflection errors are reduced, but device complexity increases due to additional impedance matching circuits
Solution Approach 1:
The impedance matching circuit is integrated into the output buffer structure, allowing the same circuit to serve dual functions: driving the output signal and providing impedance matching. The select signal mechanism enables a single circuit structure to accommodate multiple impedance requirements (100Ω, 50Ω, 25Ω) without requiring separate dedicated impedance matching circuits for each case.
Solution Approach 2:
The patent merges the impedance matching function with the output buffer circuit by integrating resistance selection switches directly into the buffer structure. This combination eliminates the need for separate external impedance matching components, reducing overall device complexity while maintaining signal transmission reliability.
3Manufacturing precision
If trimming operations are performed to control output resistance, then manufacturing precision is improved, but testing time and productivity are reduced
Solution Approach 1:
The patent implements preliminary action by pre-configuring multiple fixed resistance values (100Ω, 50Ω, 25Ω) into the circuit design, eliminating the need for complex real-time trimming operations. During manufacturing, the appropriate pre-configured resistance can be selected via simple switch configuration rather than requiring iterative measurement and adjustment, thereby maintaining manufacturing precision while significantly reducing testing time.
Data Source
AI summary
A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an impedance of the buffer circuit on a side connected to the data input/output pad. The semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage. The impedance-controlling circuit comprises a first P-channel transistor. A source terminal of the first P-channel transistor is connected to the first-supplied-voltage-supplying pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.