Multiple-Channel Memory With Independent Paths for Idle-Cycle Reduction
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Solution Overview
Problem
Chiplet systems face inefficiencies in memory device utilization due to idle data cycles caused by activate-to-activate delay requirements in memory access protocols, which limit bandwidth and reduce the effective use of memory channels.
Innovation Solution
A memory controller is configured to provide independent data and command/address signals to separate sub-portions of memory devices, allowing concurrent access to independent memory arrays through multiple channels, thereby optimizing memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory access protocols enforce activate-to-activate delay requirements, then memory device reliability is maintained, but memory channel bandwidth is reduced due to idle data cycles
Solution Approach 1:
The memory channel is segmented into multiple independent sub-channels (e.g., first and second sub-channels), each capable of independent memory access operations. This segmentation allows parallel access to different memory banks, enabling one sub-channel to remain active while another observes activate-to-activate delays, thereby maintaining overall bandwidth utilization without compromising memory device reliability
Solution Approach 2:
The patent introduces a temporal dimension to the memory access strategy by staggering activate commands across multiple sub-channels. Instead of sequential access in a single channel, the system utilizes multiple dimensions of time and channel space, allowing overlapping memory operations that effectively hide delay periods and maintain sustained bandwidth
2Device complexity
If memory access operations are performed sequentially through single channels, then device complexity is reduced, but memory device utilization efficiency deteriorates due to idle cycles
Solution Approach 1:
The memory interface is divided into multiple independent sub-interfaces or sub-channels, each handling separate memory access streams. This segmentation enables concurrent access to multiple memory banks, significantly improving device utilization efficiency while keeping each individual sub-interface relatively simple and manageable
Solution Approach 2:
Multiple simple sub-channels are merged into a unified memory interface system that operates as a single logical entity. The memory controller coordinates access across sub-channels to present a unified interface to the processor, achieving high utilization efficiency without requiring complex individual channel designs
Data Source
AI summary
A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.