Memory Index Hashing for Thread Replication Artifacts
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Solution Overview
Problem
Generating workloads that reflect large degrees of thread-level parallelism for processor simulation is challenging, as existing methods either require real systems that may not exist or result in performance differences between simulation and actual hardware, leading to inaccurate results and increased simulation time.
Innovation Solution
A method and system for generating extended instruction traces using memory index hashing, where an instruction trace representing M distinct threads is created from an existing trace of N threads by replicating threads, assigning unique identifiers, and hashing memory addresses to mitigate artifacts caused by replication, especially in shared memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If threads are replicated to generate extended instruction traces with higher parallelism, then the workload represents more threads, but artifacts are introduced that distort execution behavior
Solution Approach 1:
The patent applies local quality by differentiating memory address handling based on whether addresses map to shared memory structures. For addresses that do map to shared structures (like cache lines), the patent hashes the address to distribute replicas across different physical locations, while leaving other addresses unchanged. This selective local modification prevents artifacts in critical shared resource access while preserving original behavior elsewhere.
Solution Approach 2:
The patent introduces memory index hashing as an intermediary mechanism between thread replication and memory access. The hashing function acts as a mediator that transforms replicated thread addresses into distinct physical locations for shared memory structures, preventing direct conflicts while maintaining the logical structure of the replicated workload.
2Adaptability or versatility
If simulation is configured to generate workloads with arbitrary thread-level parallelism, then the simulator can represent more threads, but simulation time increases significantly
Solution Approach 1:
The patent uses copying by replicating existing instruction traces to create extended traces with higher thread parallelism. Instead of generating workloads from scratch or requiring real systems with many threads, the patent copies and replicates existing trace data, significantly reducing the time required to create high-parallelism workloads compared to full simulation or real-system capture.
3Productivity
If existing traces are used for simulation, then simulation can be performed, but the traces do not fully exercise processing resources due to limited thread count
Solution Approach 1:
The patent applies dynamics by making the trace representation flexible and adaptable. The system can dynamically adjust the number of threads represented in a trace by replicating existing traces, allowing the same base trace to serve multiple simulation scenarios with different parallelism levels. This dynamic scaling enables the simulation to exercise processing resources more thoroughly while maintaining productivity.
Data Source
AI summary
A method and system for trace generation using memory index hashing. A method may include generating an extended trace representative of M threads of instruction execution from a trace representative of N threads of instruction execution, where N and M are integers, N≧1 and M>N, and where each of the N threads of the trace includes memory references to respective memory addresses. Generating the extended trace from the trace may include replicating the N threads to generate the M threads, assigning a respective identifier to each of the M threads, and for a given one of the M threads, hashing a first portion of each of the respective addresses dependent upon the respective identifier of the given thread, where the first portion of each of the respective addresses corresponds to at least part of an index of a memory structure shared by at least two of the M threads.