Memory Program Inhibit Bias Selection for Stable Bitline Coupling

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Solution Overview

Problem

In memory devices, the variation in bitline-to-bitline coupling capacitance during program loops causes peak current variation and affects wordline setup time due to inconsistent application of inhibit bias voltage across bitlines.

Innovation Solution

Implementing memory device program inhibit operations with target level selection by maintaining a constant number of bitlines to which the inhibit bias is applied across program loops, using a local media controller to select a subset of program levels for inhibit bias voltage application.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If inhibit bias voltage is applied to all bitlines during program loops, then program inhibit operations are performed, but peak current variation increases due to bitline-to-bitline coupling capacitance variation

Engineering Contradiction:
Improveprogram inhibit operation consistencyVSAvoidpeak current variation
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent applies inhibit bias voltage selectively to specific bitlines based on their coupling capacitance characteristics rather than uniformly to all bitlines. The local media controller identifies bitlines with coupling capacitance below a threshold and applies inhibit bias only to those bitlines, creating a localized approach that reduces overall peak current variation while maintaining program inhibit effectiveness.

Inventive Principle:
Principle #3Local quality

2Reliability

If inhibit bias voltage is applied to all bitlines during program loops, then program inhibit operations are performed, but wordline setup time is affected due to inconsistent capacitance

Engineering Contradiction:
Improveprogram inhibit operation consistencyVSAvoidwordline setup time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements selective inhibit bias application to bitlines with coupling capacitance below a threshold, creating more consistent electrical conditions for wordline setup. By targeting only specific bitlines rather than all bitlines uniformly, the system achieves more predictable timing characteristics and reduces wordline setup time variations.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent dynamically adjusts the inhibit bias application based on coupling capacitance parameter measurements. The local media controller monitors coupling capacitance values and modifies which bitlines receive inhibit bias voltage, changing the electrical parameters to optimize both reliability and timing performance.

Inventive Principle:
Principle #35Parameter changes

3Power

If inhibit bias is applied to a constant number of bitlines, then bitline-to-bitline coupling capacitance is stabilized, but complexity increases due to selection logic

Engineering Contradiction:
Improvepeak current variationVSAvoidbitline selection logic
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The system performs self-characterization by having the local media controller measure coupling capacitance values for each bitline and automatically determine which bitlines require inhibit bias application. This self-service approach reduces the need for external configuration or complex pre-programming of selection logic, as the system adapts to its own electrical characteristics.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements a feedback mechanism where the local media controller continuously monitors coupling capacitance values and adjusts inhibit bias application accordingly. The controller uses real-time capacitance measurements to dynamically select which bitlines receive inhibit bias, creating a closed-loop system that optimizes performance based on actual electrical conditions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20260018212A1Implementing memory device program inhibit operations with target level selection
Publication Date: 2026.01.15 MICRON TECHNOLOGY INC
  • US20260018212A1 patent drawing
  • US20260018212A1 patent drawing
  • US20260018212A1 patent drawing

AI summary

A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including selecting a first group of bitlines of the memory array, the first group of bitlines corresponding to target program levels to be programmed during a program loop, selecting a second group of bitlines of the memory array, the second group of bitlines corresponding to program levels that are to be inhibited during the program loop, causing an inhibit bias voltage to be applied to the second group of bitlines, and causing a ground voltage to be applied to program the first group of bitlines during the first program loop. The second group of bitlines includes at least one bitline corresponding to a program level that has not been programmed.