Memory Initialization via Separate Data and Parity Bit Writes
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Solution Overview
Problem
Existing memory initialization methods in programmable integrated circuits (ICs) are inefficient and slow, particularly in System On Chips (SoCs) and field programmable gate arrays (FPGAs, where the memory architecture is not optimized to fully utilize available interconnect resources, leading to large configuration bitstreams and prolonged initialization times.
Innovation Solution
The proposed solution involves initializing data bits and parity bits separately within each frame of the memory, utilizing a write buffer to perform multiple write operations for data bits without writing parity bits, and vice versa, thereby maximizing the use of available storage and reducing the number of frames required for complete initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional memory initialization methods are used, then all data bits and parity bits are written together in each operation, but this results in prolonged initialization time and increased configuration bitstream size
Solution Approach 1:
The patent segments the memory write operations into two distinct phases: first writing only data bits (excluding parity bits), then writing only parity bits (excluding data bits). This segmentation allows each write operation to be more efficient by avoiding redundant parity bit writes during data initialization and vice versa, thereby reducing total initialization time and configuration bitstream size
2Loss of substance
If traditional memory initialization methods are used, then the configuration bitstream includes redundant parity bit data, but this increases the size of the configuration bitstream
Solution Approach 1:
The patent extracts and removes redundant parity bit information from the configuration bitstream by implementing separate write operations. During the first phase, only data bits are written without including parity bits. During the second phase, only parity bits are written. This extraction eliminates redundant data transmission while ensuring complete initialization through the two-phase approach
Data Source
AI summary
Circuits and methods for initializing a memory. Each row of the memory includes data bits and associated parity bits. A write buffer contains bit values for initializing the memory, and a control circuit performs a first set of write operations that write values from the write buffer to the data bits of the memory without writing values to the associated parity bits. The write buffer performs a second set of write operations that write values from the write buffer to the parity bits associated with the data bits without writing data to the data bits.