Semiconductor Memory Device Inner Source Select Transistor Threshold Voltage Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in improving the threshold voltage distribution of select transistors, which affects the reliability and performance of memory operations.
Innovation Solution
A semiconductor memory device is designed with a memory block comprising multiple string groups, where each string group includes cell strings with inner and outer source select transistors. The control logic performs a program operation on the outer source select transistors and inner source select transistors by applying a program voltage multiple times to the inner source select line, and includes a verify operation by dividing the inner source select transistors into at least two groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program operation is performed on source select transistors by applying program voltage to improve threshold voltage distribution, then the reliability of memory operations is improved, but the complexity of control logic and operation procedures increases
Solution Approach 1:
The source select transistors are divided into inner source select transistors and outer source select transistors, which are programmed separately using different control procedures. This segmentation allows the complex programming process to be broken down into manageable stages, improving reliability while making the control logic more systematic and less error-prone.
Solution Approach 2:
The outer source select transistors are programmed first before the inner source select transistors. This preliminary action establishes a foundation for subsequent operations, ensuring that the threshold voltage distribution is progressively improved in a controlled manner, thereby enhancing overall reliability without overwhelming the control logic.
Solution Approach 3:
The programming operation is performed multiple times with periodic verification steps. The control logic alternates between applying program voltage and performing verify operations, which systematically refines the threshold voltage distribution. This periodic approach improves reliability while keeping the control logic structured and repeatable.
2Manufacturing precision
If the inner source select transistors are divided into multiple groups for verify operation, then the manufacturing precision of threshold voltage control is improved, but the operation time and process complexity increase
Solution Approach 1:
The inner source select transistors are divided into multiple groups that are verified separately. This segmentation enables precise control of threshold voltage for each group, improving manufacturing precision. The grouped verification approach allows systematic control while managing operation time through organized sequencing.
Solution Approach 2:
The inner source select transistors are programmed before the verify operation is performed on each group. This preliminary programming action ensures that the threshold voltage is established before verification, allowing precise control. The sequential approach of programming followed by grouped verification optimizes both precision and time management.
Solution Approach 3:
The verify operation provides feedback on the threshold voltage distribution of each group of inner source select transistors. This feedback mechanism allows the control logic to adjust subsequent programming operations to achieve the desired precision. The iterative feedback process improves manufacturing precision while managing operation time through efficient adjustment.
Data Source
AI summary
A semiconductor memory device includes a memory block including plurality of string groups, a peripheral circuit, and control logic. The peripheral circuit performs a program operation on source select transistors included in the memory block. The control logic controls the program operation of the peripheral circuit. Each of the plurality of string groups includes at least one cell string, and the at least one cell string includes inner source select transistors located adjacent to memory cells and outer source select transistors located adjacent to a common source line. The control logic controls the peripheral circuit to perform program operations on the outer source select transistors and the inner source select transistors by an ISPP method. The control logic controls the peripheral circuit to perform a verify operation by dividing the inner source select transistors into at least two groups during the program operation of the inner source select transistors.