Memory Input Buffer Circuit for High-Voltage Signal Latching
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Solution Overview
Problem
Conventional semiconductor memory input buffer circuits face challenges in achieving fast operation and accommodating a wide range of input signals, particularly due to slower voltage increase speeds of input transistors when data input and reference voltages are high, leading to incomplete amplification and latch operations.
Innovation Solution
The proposed solution involves an input buffer circuit design with transistors and control circuits that manage intermediate voltages and capacitances to ensure timely amplification and latch operations, independent of data input signal and reference voltage levels, by using transistors with appropriate threshold voltages and capacitive configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the data input signal DQ and reference voltage VREF are increased to accommodate a wide range of input signals, then the adaptability of the input buffer is improved, but the voltage increase speed of input transistors becomes slower due to smaller VGS
Solution Approach 1:
The patent introduces an intermediate voltage generation circuit that creates an elevated voltage (e.g., VDD + Vth) to drive the gate of the input transistor. This intermediary voltage compensates for the reduced VGS when DQ and VREF are high, restoring the transistor's voltage increase speed without limiting the input signal range.
Solution Approach 2:
The patent dynamically changes the gate voltage parameter of the input transistor by adding a threshold voltage offset (Vth) to the power supply voltage (VDD). This parameter change ensures that the transistor maintains adequate driving capability across the full range of input signal voltages, particularly when DQ and VREF are at their maximum values.
2Adaptability or versatility
If conventional input buffer circuits are used with high DQ and VREF voltages, then the adaptability is improved, but the amplification and latch operations may not be completed within the clock cycle
Solution Approach 1:
The patent applies preliminary action by pre-charging the internal nodes to an elevated voltage level (VDD + Vth) before the amplification operation begins. This head start in voltage establishment reduces the time required for the amplification and latch operations to complete, ensuring timely operation even with high input voltages.
Solution Approach 2:
The intermediate voltage circuit serves as a mediator that bridges the gap between the power supply voltage and the required node voltages for complete amplification. By providing an elevated driving voltage, it enables the amplification process to complete within the available clock cycle regardless of the input signal voltage level.
3Reliability
If the voltage of nodes node1 and node2 is increased to approximately VDD to complete amplification, then the amplification completeness is improved, but the total capacitance of related capacitors is remarkably large
Solution Approach 1:
The patent changes the voltage parameter at which the amplification operates by using an elevated gate voltage (VDD + Vth). This allows the amplification to achieve completeness with smaller voltage swings at the internal nodes, thereby reducing the required capacitance values while maintaining reliable operation.
Data Source
AI summary
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and second intermediate voltages responsive to first and second input voltages; first and second voltage terminals; a circuit node; a first transistor coupled between the first voltage terminal and the circuit node and is turned on responsive to at least one of the first and second intermediate voltages; a second amplifier including first and second inverters, at least one of the first and second inverters being coupled between the circuit node and the second voltage terminal; and first and second output nodes, the first output node being coupled to an input node of the first inverter and an output node of the second inverter, and the second output node being coupled to an output node of the first inverter and an input node of the second inverter.