Memory Input Circuit Delay Path Trimming for Setup Hold Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As data transmission speeds increase, memory devices face difficulties in satisfying the input setup and hold time requirements due to manufacturing variability in input and clock delay times, making it challenging to properly capture signals in the input circuit.
Innovation Solution
The memory device incorporates an input circuit with delay paths for both input and clock signals, along with a multiplexer that selects between delayed internal clock signals based on a test mode control signal, allowing for adjustment of delay times to meet the setup and hold requirements through a trimming process during test operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased, then productivity is improved, but input setup and hold time requirements become harder to satisfy
Solution Approach 1:
The patent implements dynamic delay adjustment by providing multiple delay paths (first delay path and second delay path) with different delay amounts. The system dynamically selects between these delay paths based on whether the current data transmission speed satisfies the setup and hold time requirements, thereby adapting the delay configuration to different operating conditions to maintain reliable signal capture.
Solution Approach 2:
The patent changes the delay parameter by switching between different delay paths with different delay amounts. When the data transmission speed increases and setup/hold time requirements are no longer satisfied, the system changes the delay parameter by selecting a delay path with a larger delay amount, thereby restoring the timing relationship between input signals and clock signals.
2Reliability
If delay times are adjusted to meet setup and hold requirements, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the delay function into multiple independent delay paths, where each delay path provides a specific delay amount. This segmentation allows the system to select the appropriate delay path based on operating conditions, achieving reliable signal capture without requiring a single complex adjustable delay mechanism.
Solution Approach 2:
The patent makes the delay circuit multi-functional by designing it to serve both normal operation and test operations. The same delay circuit structure with multiple delay paths is used in both modes, with the difference being which path is selected. This universality avoids duplicating the delay circuit for test purposes, thereby reducing overall device complexity.
3Device complexity
If a single delay circuit is used for both normal and test operations, then device complexity is reduced, but test operation adaptability is limited
Solution Approach 1:
The patent implements dynamic adaptability for test operations by enabling the selection between different delay paths during test mode. The test controller can dynamically choose which delay path to use based on the specific test requirements, allowing the single delay circuit structure to adapt to various test scenarios without requiring separate dedicated test delay circuits.
Data Source
AI summary
An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch, a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and a multiplexer coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal in response to a test mode control signal, and to provide the selected signal to the data latch.