Memory Instance Renaming for IC Layout Mapping
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Solution Overview
Problem
The process of selecting and mapping user-defined memories to a base platform in integrated circuit design is complex due to the variety of customer designs and limited resources, requiring efficient tools for memory placement and layout pattern mapping.
Innovation Solution
A computer-implemented process that receives a list of design memories, associates pre- and post-placement models, and renames instances differently to map them to an integrated circuit layout pattern, using a universal memory tool that includes memory editing, pre-placement model generation, placement, and post-placement model generation tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If user-defined memories are mapped to pre-defined memory locations on a base platform, then the integrated circuit can be implemented with standardized components, but the mapping process becomes complex due to variety of customer designs and limited resources
Solution Approach 1:
The patent segments the memory mapping process into distinct phases: pre-placement model generation, placement mapping, and post-placement model generation. Each phase handles specific aspects of the mapping problem, dividing the complex overall task into manageable segments that can be processed systematically.
Solution Approach 2:
The patent performs preliminary actions by generating pre-placement models before the actual mapping process. These models contain anticipated mapping configurations that guide the placement tool, preparing the system in advance to handle the variety of customer designs efficiently.
Solution Approach 3:
The patent changes parameters by renaming memory instances after placement based on their specific mapping configurations. This parameter change (renaming) distinguishes between differently-mapped instances of the same memory type, enabling precise tracking and management of diverse memory mappings across various customer designs.
2Adaptability or versatility
If multiple instances of the same memory type are mapped differently to accommodate various design requirements, then design flexibility is improved, but tracking and managing each instance becomes more difficult
Solution Approach 1:
The patent applies local quality by giving each memory instance its own specific characteristics through renaming. After placement, instances that are mapped differently receive unique names that reflect their local mapping qualities, allowing each instance to be tracked according to its specific configuration rather than using generic type names.
Solution Approach 2:
The patent uses parameter changes (renaming) to encode mapping information directly into the instance identifiers. This transformation maintains design flexibility while preventing loss of tracking information, as each renamed instance carries its own mapping history and configuration details.
3Manufacturing precision
If precise timing and layout models are generated for each memory type after placement, then manufacturing precision is improved, but the post-processing step increases overall process complexity
Solution Approach 1:
The patent performs preliminary model generation before placement, creating templates that anticipate the mapping configurations. This preliminary action reduces the complexity of post-processing by pre-establishing the framework for timing and layout analysis, so that post-placement model generation becomes a refinement step rather than a complex creation process.
Solution Approach 2:
The patent uses parameter changes (instance renaming) to organize memory instances in a way that facilitates efficient post-placement model generation. By grouping and identifying instances according to their mapping characteristics, the system prepares the data structure to enable precise timing and layout modeling with minimal additional processing complexity.
Data Source
AI summary
A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.