Nonvolatile Memory Insulating Film Thickness Control
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Solution Overview
Problem
As memory cells in NAND type flash memories are miniaturized, the diffusion of oxidizers during the oxidizing process affects the intergate insulating films, leading to 'bird's beaks' and reduced dielectric constants, while the use of multilayer insulating films increases parasitic capacitance, causing threshold voltage variations and performance degradation.
Innovation Solution
The implementation of a multilayer intergate insulating film structure with a thinner lowermost layer on the isolation insulating layer, reducing parasitic capacitance and suppressing the diffusion of fixed charges, thereby improving the write characteristics and preventing characteristic deterioration of memory cells and peripheral transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a NONON film (multilayer intergate insulating film) is used to prevent oxidizer diffusion and protect memory cell performance, then the dielectric constant is improved and element performance is protected, but parasitic capacitance between adjacent floating gate electrodes increases causing threshold voltage variation
Solution Approach 1:
The patent applies local quality by making the lowermost silicon nitride film thickness non-uniform: it is formed to be thinner in the region corresponding to the floating gate electrode compared to other regions. This localized thickness variation reduces parasitic capacitance between adjacent floating gate electrodes while maintaining the protective function of the NONON structure where needed.
Solution Approach 2:
The patent changes the physical parameter of film thickness specifically for the lowermost silicon nitride film in the NONON structure. By controlling and varying the thickness parameter of this specific layer, the patent achieves reduced parasitic capacitance while preserving the essential protective functions of the multilayer insulating structure.
2Productivity
If memory cells are miniaturized to increase integration, then higher integration is achieved, but oxidizer diffusion into the ONO film increases causing bird's beak formation and reduced dielectric constant
Solution Approach 1:
The patent applies preliminary action by forming the complete NONON multilayer structure before the oxidizing process. The lowermost silicon nitride film is deposited in advance to serve as a protective barrier that prevents oxidizer diffusion into the underlying silicon oxide film and floating gate electrode, thereby preventing bird's beak formation before it can occur.
Solution Approach 2:
The patent uses composite materials by constructing the intergate insulating film as a NONON multilayer structure consisting of alternating silicon nitride and silicon oxide films. This composite structure combines the oxidation resistance of silicon nitride with the dielectric properties of silicon oxide, providing both protection against oxidizer diffusion and maintaining electrical performance.
3Object-generated harmful factors
If the lowermost silicon nitride film is made thinner to reduce parasitic capacitance, then threshold voltage variation is reduced, but the protective function against oxidizer diffusion may be compromised
Solution Approach 1:
The patent applies local quality by making the lowermost silicon nitride film thickness non-uniform: it is formed to be thinner in the region corresponding to the floating gate electrode compared to other regions. This localized thickness variation reduces parasitic capacitance between adjacent floating gate electrodes while maintaining the protective function of the NONON structure where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and threshold voltage variations, enhancing the write characteristics of memory cells and maintaining the performance of peripheral transistors by controlling the thickness of the intergate insulating films.
Implementation Method 1
an insulating film serving as a lowermost layer of the first intergate insulating film on the first isolation insulating layer is thinner than an insulating film serving as a lowermost layer of the second intergate insulating film on the second isolation insulating layer
Implementation Method 2
the miniaturization of the memory cell causes another problem that inter-cell interference is induced by parasitic capacitance between the adjacent floating gate electrodes
Data Source
AI summary
A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.