Semiconductor Memory Insulating Layer CMP Hard Mask Strategy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory device manufacturing methods face challenges in forming high-density insulating layers with excellent mechanical strength, particularly as device miniaturization increases, leading to issues with pitch reduction and potential structural height differences during the CMP process.
Innovation Solution
The method involves forming a laminated body with conducting, barrier conducting, and chalcogen layers on the substrate, using hard mask layers to create line and space patterns, and employing polysilazane for insulating layer formation, with specific processes to maintain hard mask layers in critical areas to prevent excessive etching and ensure accurate pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device miniaturization is pursued to increase memory density, then memory capacity increases, but pitch reduction leads to structural height differences and manufacturing precision deteriorates
Solution Approach 1:
The patent applies local quality by forming different insulating layer structures in different regions: in the first area, a first insulating layer is formed with specific thickness, while in the second area, a second insulating layer is formed with different thickness characteristics. This regional differentiation allows optimization of each area's properties to maintain manufacturing precision while achieving high memory density through pitch reduction.
Solution Approach 2:
The patent segments the substrate into multiple areas (first area and second area) with different insulating layer configurations. This segmentation allows independent optimization of each region's characteristics, enabling the formation of high-density memory structures without compromising overall manufacturing precision and pattern accuracy.
2Quantity of substance
If insulating layer thickness is reduced to achieve higher density, then pitch is reduced, but mechanical strength and reliability of the insulating layer deteriorate
Solution Approach 1:
The patent employs composite material strategy by forming multiple insulating layers (first insulating layer and second insulating layer) with different thicknesses and properties in different areas. This composite approach allows the system to achieve high overall density while maintaining mechanical strength through the combined properties of multiple layers, where each layer can be optimized for specific functions.
Solution Approach 2:
Different insulating layers are formed with locally optimized thicknesses and materials: the first insulating layer in the first area provides base insulation, while the second insulating layer in the second area provides additional mechanical support. This local quality differentiation ensures that density requirements are met without compromising overall structural reliability.
3Shape
If CMP process is used to flatten the substrate, then surface uniformity is improved, but hard mask layers may be excessively etched causing pattern breaks
Solution Approach 1:
The patent applies preliminary action by strategically maintaining hard mask layers in the second area before the CMP process. These pre-positioned hard mask layers serve as protective elements that prevent excessive etching during CMP, ensuring pattern integrity is preserved while still achieving the necessary surface uniformity for high-density structure formation.
Solution Approach 2:
The hard mask layers act as intermediary protective elements during the CMP process. By maintaining these layers in critical areas, they serve as mediators that protect the underlying patterns from excessive etching while allowing the CMP process to achieve the required surface uniformity, thus resolving the contradiction between flattening and pattern preservation.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a substrate including a first area, a second area, and a third area, the second and the third areas being adjacent to the first area; a first insulating layer disposed in the first to the third areas; a first wiring disposed on a surface of the first insulating layer in the first area; a first memory cell disposed on the first wiring; a second wiring disposed on the first memory cell; and a contact connected to the second wiring in the second area. The surface of the first insulating layer includes: first surfaces disposed in at least one of the second area and the third area and arranged in the first direction; and second surfaces disposed between the first surfaces. The second surfaces are close to or far from the substrate compared with the first surfaces.