Non-Volatile Memory Insulating Layer Thickness Design
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Solution Overview
Problem
Conventional non-volatile memory devices experience a second-bit effect, where one bit's storage affects the reading of another, reducing device reliability and making multi-level cell memory operations difficult, due to the direct impact on threshold voltage and sense margin.
Innovation Solution
A non-volatile memory fabrication method involving a stacked structure with a non-uniform insulating layer thickness, where the peripheral region has a greater thickness than the internal region, reducing drain-induced barrier lowering and thereby mitigating the second-bit effect, and enhancing the voltage threshold window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform thickness insulating layer is used in conventional non-volatile memory, then the manufacturing process is simple, but the second-bit effect occurs reducing device reliability
Solution Approach 1:
The insulating layer is designed with non-uniform thickness where the peripheral region has greater thickness than the internal region. This local variation in thickness creates different electrical characteristics at different locations, reducing the second-bit effect by isolating the electric fields of adjacent memory bits while maintaining overall structural integrity.
Solution Approach 2:
The solution transitions from a uniform two-dimensional insulating layer to a three-dimensional non-uniform structure with varying thickness. This dimensional change allows the peripheral region to provide additional electrical isolation without increasing lateral dimensions, effectively mitigating the second-bit effect.
2Reliability
If drain voltage is increased to enhance DIBL, then the barrier and threshold voltage from second-bit effect are reduced, but device dimension shrinkage causes operation difficulties
Solution Approach 1:
The insulating layer thickness is changed as a structural parameter to control electrical characteristics. By increasing the peripheral thickness, the effective barrier height is enhanced through geometric configuration rather than voltage adjustment, allowing operation at lower drain voltages while maintaining threshold stability.
3Reliability
If the peripheral region of the insulating layer has greater thickness, then the second-bit effect is reduced, but the manufacturing precision requirement increases
Solution Approach 1:
The non-uniform insulating layer structure is formed as a preliminary step before memory bit formation. By pre-establishing the thickness variation pattern, subsequent processing steps work with this fixed geometric configuration, reducing the need for high-precision thickness control during later manufacturing stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the second-bit effect, increases the voltage threshold window, and improves the reliability of memory devices, enabling more reliable multi-bit memory operations.
Implementation Method 1
A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer
Data Source
AI summary
A method for fabricating a non-volatile memory is provided. The method includes a stacked structure and a consuming layer are formed in sequence over a substrate. A converting process is performed at a peripheral region of the consuming layer to form a first insulating layer. A conductive layer is formed over the stacked layer and the first insulating layer.