Nonvolatile Memory Insulating Layer Trap Density Gradient
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Solution Overview
Problem
In nonvolatile semiconductor memory elements, thinner upper insulating layers lead to increased leak current and degraded write and erase operations, causing threshold fluctuations due to electron emission during data retention, which existing solutions fail to adequately address.
Innovation Solution
A nonvolatile semiconductor memory element with a three-layer or two-layer upper insulating structure, comprising a transmitting layer, a trapping layer with high electron trap level density, and a blocking layer, where the trapping layer's electron trap level density is greater than that of the blocking layer, to effectively trap and release electrons during writing and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the upper insulating layer is made thinner to accommodate miniaturization, then the device can be scaled down, but the leak current increases and write/erase operations are degraded
Solution Approach 1:
The upper insulating layer is divided into multiple sub-layers (first upper insulating layer, second upper insulating layer, third upper insulating layer) with different trap level densities. The first layer has high trap density for electron capture, the second layer has intermediate density, and the third layer has low density. This segmentation allows each layer to perform specific functions: capturing electrons during write, holding them during retention, and enabling efficient erase, thereby reducing leak current while maintaining device scalability.
Solution Approach 2:
Different regions of the upper insulating layer are given different local properties through varying trap level densities. The first upper insulating layer (near the charge storage layer) has high trap density to efficiently capture electrons during write operations. The second layer has intermediate density for moderate electron holding. The third layer (near the control gate) has low density to facilitate electron emission during erase operations. This local quality differentiation resolves the contradiction by optimizing each region's function.
2Volume of moving object
If the upper insulating layer is made thinner, then device scaling is enabled, but write operation efficiency is degraded due to increased leak current
Solution Approach 1:
The upper insulating layer is segmented into three distinct layers with progressively decreasing trap level densities from the charge storage layer toward the control gate. This segmentation enables the first layer to efficiently capture electrons during write operations while the thinner overall structure allows device scaling. The multi-layer structure maintains write efficiency by providing dedicated electron capture zones without requiring a thick insulating layer.
3Volume of moving object
If the upper insulating layer is made thinner, then device scaling is enabled, but erasing efficiency is degraded due to increased electron injection from control gate
Solution Approach 1:
The third upper insulating layer (closest to the control gate) is designed with low trap level density to facilitate efficient electron emission during erase operations. This local quality optimization at the control gate interface enables electrons to be readily injected into the charge storage layer during erase, maintaining erasing efficiency even with a thinner overall insulating layer structure that enables device scaling.
4Reliability
If electrons are trapped in the upper insulating layer to reduce leak current, then reliability is improved, but threshold fluctuation occurs due to electron emission during data retention
Solution Approach 1:
The upper insulating layer is segmented into three layers with different trap level densities to create a stable electron distribution during data retention. The first layer (high trap density) captures and holds electrons firmly, preventing them from emitting to the charge storage layer. The second layer (intermediate density) provides a transition zone. The third layer (low density) near the control gate allows controlled electron emission. This segmentation stabilizes the threshold voltage by preventing unwanted electron emission while maintaining low leak current.
Solution Approach 2:
The trap level density parameter is varied across the thickness of the upper insulating layer, creating a gradient from high to low density. This parameter change ensures that electrons trapped near the charge storage layer (in the first layer with high trap density) remain stable during data retention and do not emit, thereby maintaining threshold voltage stability while still achieving low leak current characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure suppresses charge emission from the upper insulating layer during data retention, reducing threshold fluctuations and enhancing the reliability of the memory element by effectively trapping and detrapping electrons, thereby improving the write and erase operations.
Implementation Method 1
a first insulating film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film
Implementation Method 2
a detrap pulse is applied after data is written into a nonvolatile semiconductor memory element. The detrap pulse is applied, whereby the charge trapped in the upper insulating layer at the write operation can be pulled out
Data Source
AI summary
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.