Memory Integrity Checking with Parallel Checksum Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory protection mechanisms in electronic equipment are inefficient, leading to significant performance losses and increased chip area requirements, while current integrity checking methods fail to effectively detect changes caused by attacks or spontaneous errors without disrupting normal operations.
Innovation Solution
A semiconductor chip apparatus with an integrity checking device that calculates and updates checksums in parallel with memory access, using a dual-port memory or timing mechanisms to ensure simultaneous access, thereby minimizing performance loss and chip area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory integrity checking methods are used, then memory integrity can be verified, but processing must be suspended causing performance loss
Solution Approach 1:
The patent implements continuous integrity checking by calculating checksums in parallel with memory access operations. The dual-port memory allows the integrity checking device to read memory contents and compute checksums simultaneously while the memory access element performs normal read/write operations, eliminating the need to suspend processing for integrity verification.
Solution Approach 2:
The patent pre-calculates checksums for memory locations before they are accessed by the memory access element. The integrity checking device continuously updates checksums for memory locations that will be accessed next, so that when the memory access element needs to verify integrity, the checksums are already ready, eliminating verification delay.
2Reliability
If comprehensive memory protection mechanisms are implemented, then security against attacks is improved, but chip area requirements increase
Solution Approach 1:
The patent divides the memory system into two independent ports: a memory access element port for normal operations and an integrity checking device port for verification operations. This segmentation allows both functions to operate simultaneously on the same memory array without requiring duplicate memory structures, thus providing comprehensive protection while minimizing additional chip area.
Solution Approach 2:
The dual-port memory structure serves multiple functions: it enables simultaneous normal memory access and integrity checking operations, allows the same memory array to be used for both data storage and verification purposes, and provides both security protection and performance maintenance without requiring separate dedicated verification memory.
3Productivity
If parallel integrity checking is implemented using dual-port memory, then processing continuity is maintained, but device complexity increases
Solution Approach 1:
The patent combines the integrity checking function with the existing memory structure by implementing a dual-port memory where one port handles normal access and the other handles verification. This merging approach integrates the checking mechanism into the memory itself rather than adding separate verification hardware, reducing overall system complexity while maintaining processing continuity.
Data Source
AI summary
A semiconductor chip apparatus including a memory having a plurality of memory locations, a memory access element, and an integrity check device configured to store a reference value for a check function over values stored in the memory locations and, in a case of write access to a memory location, configured to update a check value with the value to be written by the write access if the check value represents the value stored in the memory location prior to the write access, and configured to compare the reference value with the check value after the check value has been generated and output a signal depending on a result of the comparison.