Memory Integrity Check via Segmented Error Detection
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Solution Overview
Problem
Electronic devices face vulnerabilities in memory integrity due to potential attacks and spontaneous errors, which can compromise secret data and device functionality, necessitating effective protection mechanisms.
Innovation Solution
A data processing device with an associated error detection memory area for each memory location, a memory control device for storing error detection codes, and an integrity checking device that generates and compares checksums to detect changes, combining error detection codes with checksum calculations to ensure memory integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection codes are stored for each memory location, then memory integrity detection capability is improved, but device complexity and memory overhead increase
Solution Approach 1:
The memory system is segmented into memory locations with associated error detection memory areas. Each memory location has its own dedicated error detection code stored in a separate error detection memory area, allowing independent verification of each location without affecting others. This segmentation enables granular integrity checking while maintaining modular complexity management.
Solution Approach 2:
Error detection codes serve as intermediary elements between the memory locations and the integrity checking mechanism. These codes act as mediators that encode information about the expected state of memory locations, enabling the checking device to verify integrity without directly analyzing the entire memory content. This intermediary layer simplifies the checking process while maintaining comprehensive coverage.
2Reliability
If checksum verification is performed on all memory locations, then detection of unauthorized changes is improved, but processing time and productivity decrease
Solution Approach 1:
Error detection codes are pre-calculated and stored in error detection memory areas before the actual memory writing operation occurs. The memory control device generates these codes in advance based on the data to be written, so that when integrity checking is needed, the verification process can proceed quickly by comparing pre-computed codes rather than performing complex checksum calculations on the entire memory content at verification time.
Solution Approach 2:
The system changes the parameter of verification from computing full checksums over memory locations to comparing pre-stored error detection codes. This parameter change transforms a computationally intensive operation into a simple comparison operation, dramatically reducing the time required for integrity verification while maintaining detection capability.
3Reliability
If error detection codes are checked during write access, then protection against manipulation is improved, but access speed and productivity decrease
Solution Approach 1:
The error detection code checking is performed as a preliminary action during the write access sequence. The memory control device verifies the error detection code of the source memory location before executing the write operation, ensuring that only valid data is transferred. This preliminary check integrates seamlessly into the write protocol without requiring separate verification passes, minimizing impact on overall access speed.
Solution Approach 2:
The error detection code checking operation is merged with the existing write access protocol. The verification of error detection codes is combined with the data transfer operations, so that the same control logic and circuitry used for managing write accesses also performs the integrity verification. This merging eliminates the need for separate verification steps and reduces overhead.
Data Source
AI summary
A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.