Memory Interconnect Error Coding and Retry Under BER Limits
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Solution Overview
Problem
In memory systems, achieving low bit-error-rate (BER) communication becomes increasingly difficult due to signaling and circuit limitations, especially as data rates increase, leading to challenges in developing faster interfaces with low BER without significant cost and complexity.
Innovation Solution
A memory controller with error detection and correction capabilities, dynamically adding error detection and correction codes to data, and performing retry remedial actions when errors are detected, allowing for improved data transmission rates with reduced BER.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rates are increased to achieve higher bandwidth, then productivity is improved, but reliability deteriorates due to increased noise and signaling limitations
Solution Approach 1:
The patent applies preliminary action by proactively adding error detection and correction codes to data packets before transmission. The memory controller predicts potential transmission errors and pre-equips data with protective coding mechanisms, allowing errors to be detected and corrected without retransmission, thus maintaining high data rates while improving reliability
Solution Approach 2:
The patent implements feedback through acknowledgment packets sent from the memory device back to the controller. When data is successfully received and decoded, the device sends an acknowledgment; if errors persist despite correction attempts, a negative acknowledgment triggers retransmission. This feedback loop enables the system to adapt to channel conditions and maintain reliability at high data rates
2Reliability
If error protection mechanisms are added to reduce BER, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the level of error protection applied to different data packets based on channel conditions and packet importance. The system can vary coding rates, packet sizes, and protection levels to optimize the balance between reliability and complexity for different operational scenarios
Solution Approach 2:
The patent segments data transmission into discrete packets with individual error protection codes. Each packet is independently encoded, transmitted, and decoded, allowing errors to be contained to specific packets rather than affecting the entire data stream. This segmentation enables selective retransmission of only erroneous packets, reducing overall complexity compared to protecting entire data streams
3Reliability
If retry mechanisms are implemented to correct errors, then reliability is improved, but loss of time increases due to retransmission delays
Solution Approach 1:
The patent applies preliminary action by pre-equipping data packets with error correction codes before transmission. This allows the receiving memory device to automatically correct errors in the time domain, eliminating the need for time-consuming retransmission cycles. The correction happens in-place during the normal data reception timeline
Solution Approach 2:
The patent introduces error correction codes as an intermediary mechanism between transmitter and receiver. These codes act as a mediator that enables automatic error correction without requiring direct interaction or retransmission between the memory controller and device, thus avoiding the time loss associated with retry protocols
Data Source
AI summary
A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.