3D Memory Interconnect Layout for Low-Capacitance Bit Lines
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Solution Overview
Problem
Current memory devices with three-dimensional memory structures face challenges in efficiently integrating bit lines and maintaining low parasitic capacitance, which can lead to increased chip size and reduced memory capacity.
Innovation Solution
The memory device employs a configuration with in-plane and out-plane interconnects, where in-plane interconnects are aligned within memory chips and out-plane interconnects pass through the stacked interconnect structure, allowing for dispersed contact arrangement and reduced parasitic capacitance, enabling efficient bit line routing and increased memory capacity without enlarging the chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is provided in a separate chip from the peripheral circuit, then the memory capacity and degree of integration are increased, but the bonding process becomes more complex and the overall device complexity increases
Solution Approach 1:
The patent merges the memory chip and peripheral circuit chip into a single integrated structure. The bit line extends from the memory cell array through the peripheral circuit region, eliminating the need for separate bonding processes and reducing overall device complexity while maintaining high memory capacity
Solution Approach 2:
The bit line transitions from a two-dimensional planar configuration to a three-dimensional structure that extends vertically through multiple layers and horizontally across different functional regions. This dimensional transition allows the bit line to connect memory cells to peripheral circuits without requiring separate chips, thereby reducing bonding complexity
2Quantity of substance
If a three-dimensional memory structure is provided in a separate chip from the peripheral circuit, then the memory capacity is increased, but the overall integration efficiency is reduced
Solution Approach 1:
The patent combines memory and peripheral circuits in a single chip, improving integration efficiency by eliminating inter-chip bonding processes while maintaining high memory capacity through three-dimensional memory structures
3Quantity of substance
If multiple conductor layers are used for bit lines in a three-dimensional memory structure, then the memory capacity and integration are improved, but the parasitic capacitance of the bit line increases
Solution Approach 1:
The bit line is segmented into multiple conductor layers, with each layer serving a specific function. The first conductor layer forms bit lines for memory cell access, while the second conductor layer provides extended bit lines for peripheral circuit connections. This segmentation allows optimization of each layer to reduce parasitic capacitance while maintaining high memory capacity
Solution Approach 2:
Different conductor layers are optimized with different properties suited to their specific functions. The first conductor layer is optimized for high-density memory cell connections, while the second conductor layer is optimized for peripheral circuit interfacing, thereby reducing overall parasitic capacitance while maintaining memory capacity
Data Source
AI summary
A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.