Memory Device Interconnect Charge Shear Equalization
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Solution Overview
Problem
Current memory devices face challenges in reducing power consumption due to increased parasitic capacitance and interconnect charging energy, especially as element sizes shrink and memory cell arrays grow, leading to inefficiencies in write and read operations.
Innovation Solution
The memory device employs a configuration where array layers in different memory blocks are operated in parallel, with charge shear techniques used to precharge bit lines and word lines, setting potentials between voltage levels to minimize energy consumption and reduce noise from capacitance imbalances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If element sizes are shrunk and memory cell arrays are grown to increase capacity, then storage density is improved, but parasitic capacitance and interconnect charging energy increase leading to higher power consumption
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block, second memory block, etc.), each with independent bit lines and word lines. This segmentation allows selective operation of individual blocks, enabling charge shear operations to be performed on specific blocks without affecting others, thereby reducing overall power consumption while maintaining high storage density.
Solution Approach 2:
The equalization circuit performs preliminary charge shear operations on bit lines and word lines before actual memory read/write operations. By pre-charging interconnects to intermediate voltage levels and equalizing charge distribution, the circuit minimizes the energy required for subsequent high-speed operations, addressing the power consumption issue while preserving storage capacity.
2Ease of operation
If interconnect charging is performed traditionally without charge shear, then operational simplicity is maintained, but power consumption increases due to capacitance imbalances
Solution Approach 1:
The equalization circuit acts as an intermediary between traditional memory operations and the physical interconnects. It introduces charge shear operations that mediate the charging process, balancing charge distribution across bit lines and word lines before data operations. This intermediary mechanism reduces power consumption from capacitance imbalances while maintaining ease of operation through automated control.
Solution Approach 2:
The equalization circuit dynamically changes voltage parameters of interconnects by applying charge shear operations. It adjusts bit line and word line voltages to intermediate levels, equalizes charge distribution, and optimizes potential differences before memory operations. These parameter changes reduce the energy required for interconnect charging while maintaining operational simplicity.
3Use of energy by moving object
If charge shear operations are implemented to reduce power consumption, then energy efficiency is improved, but device complexity increases due to additional equalization circuits
Solution Approach 1:
The equalization circuit is designed to perform multiple functions: charge shear operations on both bit lines and word lines, equalization of charge distribution, and preparation for subsequent memory operations. By consolidating these functions into a single circuit structure that operates across multiple memory blocks, the design achieves energy efficiency while limiting the increase in device complexity through functional integration.
Solution Approach 2:
The equalization circuit performs self-service by automatically equalizing charge distribution and preparing interconnects for operations without requiring external intervention. The circuit monitors and adjusts voltage levels on bit lines and word lines autonomously, reducing the need for additional control logic and minimizing the increase in device complexity while improving energy efficiency.
Data Source
AI summary
According to one embodiment, a device includes a first cell between first and second interconnects; a second cell between second and third interconnects; a third cell between fourth and fifth interconnects; a fourth cell between fifth and sixth interconnects; a equalization circuit connected to the first to sixth interconnects; and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.