Semiconductor Memory Interconnect Layout for Low-Resistance Line Contact

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Solution Overview

Problem

Current semiconductor memory devices face challenges in improving operating characteristics and simplifying fabrication processes, particularly in achieving efficient contact between lines in the peripheral circuit regions due to differences in pattern density, leading to increased resistances and complexity in manufacturing.

Innovation Solution

The proposed solution involves a semiconductor memory device structure with a substrate having a cell region and peripheral circuit regions, where specific lines and memory cells are arranged to intersect, and the height of contact plugs is increased to facilitate contact between lines, improving current delivery and reducing resistances, thereby enhancing operating characteristics and simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication processes are used with standard contact plug heights, then manufacturing complexity is reduced, but sheet resistance increases and current delivery becomes inefficient

Engineering Contradiction:
Improvecurrent delivery efficiencyVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the height parameter of the contact plug to resolve the contradiction. By increasing the contact plug height from conventional levels to a height that extends above the upper surface of the upper interlayer insulating layer, the invention improves current delivery efficiency and reduces sheet resistance while maintaining fabrication process simplicity, eliminating the need for additional polishing steps.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If additional polishing steps are added to reduce sheet resistance, then electrical characteristics improve, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention performs preliminary action by designing the contact plug height in advance to extend above the upper surface of the upper interlayer insulating layer before any polishing steps. This preliminary structural design ensures good electrical contact and low sheet resistance without requiring subsequent polishing operations, thereby improving electrical characteristics while maintaining manufacturing simplicity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and eliminates the additional polishing step from the manufacturing process. By designing the contact plug to naturally extend above the insulating layer surface, the invention removes the need for CMP or other polishing operations that would otherwise be required to achieve the necessary contact height, thus simplifying manufacturing while maintaining electrical performance.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If contact plug height is increased to improve current delivery, then sheet resistance decreases, but fabrication complexity increases

Engineering Contradiction:
Improvesheet resistanceVSAvoidcontact plug structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by increasing the height dimension of the contact plug structure. This single parameter change achieves lower sheet resistance and improved current delivery efficiency without introducing additional structural complexity, as the contact plug maintains its basic cylindrical or rectangular shape while simply extending higher to protrude above the upper interlayer insulating layer surface.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11903220B2Electronic device and method for fabricating the same
Publication Date: 2024.02.13 SK HYNIX INC
  • US11903220B2 patent drawing
  • US11903220B2 patent drawing
  • US11903220B2 patent drawing

AI summary

A semiconductor memory includes a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and a first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein portions of the third line located in the cell region and over the contact plug contact the second line, and part of a remainder of the third line is spaced apart from the second line.