Semiconductor Memory Device Interconnect Resistance Reduction
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Solution Overview
Problem
In stacked type semiconductor memory devices, increasing the arrangement density of semiconductor members leads to an undesirable increase in the resistance value of the interconnect layer, hindering the integration of memory cell transistors.
Innovation Solution
The semiconductor memory device incorporates a stacked body with alternately arranged insulating and interconnect layers, where columnar members and insulating members are used to create a mesh-like configuration of interconnect layers, with highway, bridge, and finger portions made of different conductive materials, allowing for low-resistance pathways and high integration of memory cell transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the arrangement density of semiconductor members is increased to increase integration of memory cell transistors, then the integration density is improved, but the resistance value of the interconnect layer increases
Solution Approach 1:
The interconnect layer is segmented into multiple conductive regions (first conductive region, second conductive region, third conductive region) that are spatially separated and connected through vertical interconnects. This segmentation allows each region to be independently optimized for conductivity while maintaining overall low resistance, resolving the contradiction between high integration density and low interconnect resistance
Solution Approach 2:
The patent transitions from a two-dimensional interconnect layout to a three-dimensional structure by adding vertical conductive regions that extend through multiple interconnect layers. This dimensional change enables low-resistance pathways in the vertical direction while maintaining high horizontal integration density, simultaneously achieving both goals
Data Source
AI summary
A semiconductor memory device includes first and second insulating plates, a stacked body provided between the first insulating plate and the second insulating plate, and a semiconductor member. The stacked body includes interconnect layers. The interconnect layer includes a first interconnect portion contacting the first insulating plate, a second interconnect portion contacting the second insulating plate, a third interconnect portion, a fourth interconnect portion, fifth and sixth interconnect portions are separated from the first and the second insulating plates. The fifth interconnect portion is connected to the first interconnect portion via the third interconnect portion, and is insulated from the second interconnect portion. The sixth interconnect portion is connected to the second interconnect portion via the fourth interconnect portion, and is insulated from the first interconnect portion. The semiconductor member is disposed between the fifth interconnect portion and the sixth interconnect portion.