3D Memory Cell Interconnect Layout Without Staircase Areas
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Solution Overview
Problem
Current semiconductor structures face challenges in improving integration level due to wasted space in staircase areas and limitations in the number of stacked layers of memory cells, which hinder performance enhancement.
Innovation Solution
A semiconductor structure design that directly connects leading wire posts with horizontal signal lines, either in parallel or overlapping configurations, eliminating the need for staircase areas, thereby optimizing space utilization and reducing the number of connection layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional staircase area connection method is used, then memory cells can be connected to peripheral circuits, but space is wasted and integration level is limited
Solution Approach 1:
The patent merges the leading wire posts and horizontal signal lines into a single integrated structure. The leading wire posts extend through multiple layers and directly contact the horizontal signal lines, eliminating the need for separate staircase connection areas. This consolidation reduces wasted space and improves integration level while maintaining the necessary electrical connections between memory cells and peripheral circuits.
Solution Approach 2:
The patent transitions from a planar two-dimensional connection approach to a three-dimensional vertical connection approach. Leading wire posts extend in the vertical direction through multiple layers of memory cells, enabling connections in the third dimension. This dimensional change allows signal lines to be routed through the stack height rather than requiring lateral staircase paths, thereby improving space utilization and reducing the footprint of connection structures.
2Productivity
If the number of stacked layers of memory cells is increased, then integration level improves, but process limitations prevent further stacking
Solution Approach 1:
The patent segments the connection structure into modular leading wire posts that can be independently formed and positioned at different heights. Each leading wire post serves as an independent vertical interconnect, allowing the memory stack to be divided into manageable layers. This segmentation enables the manufacturing process to handle each layer or group of layers separately, reducing process complexity while allowing for increased total stacking height and improved integration level.
Data Source
AI summary
A semiconductor structure comprises a substrate, wherein the substrate is provided with a stacked structure, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, the stacked structure further comprising a plurality of horizontal signal lines arranged in the second direction, wherein each of the horizontal signal lines is in contact with one layer of the memory cells; and a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines.