Memory Interconnect Routing for Non-Blocking Multi-Channel Access

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing integrated circuit (IC) devices face challenges in supporting high-speed memory devices with increased channels, leading to higher circuit area and power requirements, which increase manufacturing costs.

Innovation Solution

The IC devices incorporate interleaving switch circuitries, network switch circuitries, and crossbar circuitries to facilitate non-blocking access to memory devices, reducing circuit area and power consumption by partitioning communication lanes and optimizing memory command routing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of crossbar circuitries is increased to support high-speed memory devices with increased channels, then the memory access capability is improved, but the circuit area and power requirements increase

Engineering Contradiction:

Improvememory access capabilityVSAvoidcircuit area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent divides the interconnect circuitry into multiple crossbar circuitries, each handling specific memory channels. This segmentation allows the system to support high-speed memory devices with increased channels by distributing the access load across multiple smaller crossbar units rather than requiring one large crossbar, thereby improving memory access capability while managing circuit area more efficiently

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical interconnect architecture that adds dimensional organization to the crossbar circuitries. By organizing crossbar units in a multi-level structure with different tiers handling different levels of traffic, the system achieves enhanced memory access capability without linearly increasing the area of individual crossbar units

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If the number of crossbar circuitries is increased to support high-speed memory devices with increased channels, then the memory access capability is improved, but the power requirements increase

Engineering Contradiction:

Improvememory access capabilityVSAvoidpower requirements

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the interconnect circuitry into multiple crossbar circuitries that can be independently controlled and powered. This allows the system to activate only the necessary crossbar units based on current memory access requirements, improving memory access capability while reducing overall power consumption compared to having all crossbar units continuously active

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control mechanisms that allow the interconnect circuitry to adapt its operation based on real-time memory access patterns. The system can dynamically enable or disable specific crossbar circuitries and adjust their operational parameters, thereby achieving high memory access capability when needed while minimizing power consumption during lower-demand periods

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If the number of ingress ports and egress ports is increased in crossbar circuitries, then the non-blocking access capability is improved, but the device complexity increases

Engineering Contradiction:

Improvenon-blocking access capabilityVSAvoiddevice complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the interconnect circuitry into multiple crossbar circuitries, each with a manageable number of ingress and egress ports. This segmentation provides non-blocking access capability by ensuring that each crossbar unit has sufficient ports to handle its assigned traffic without creating bottlenecks, while keeping the complexity of individual crossbar units at manageable levels

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical organization of crossbar circuitries that adds dimensional structure to the interconnect architecture. By arranging crossbar units in multiple tiers with systematic interconnections, the system achieves high non-blocking access capability through the hierarchical routing paths rather than requiring each individual crossbar to have an excessive number of ports

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12474866B2Interconnect circuitry for multi-channel and multi-requester memory systems

Publication Date: 2025.11.18 XILINX INC

AI summary

An integrated circuit device includes interconnect circuitry. The interconnect circuitry includes interleaving switch circuitries, network switch circuitries, and crossbar circuitries. The interleaving switch circuitries are coupled to requester devices. A first interleaving switch circuitry includes first ports. The first interleaving switch circuitry receives a first memory command, and outputs the first memory command via first communication lanes connected to a first port based on a memory address of the first memory command. The network switch circuitries are connected to the interleaving switch circuitries. A first network switch circuitry is connected to the first communication lanes and route the first memory command along the first communication lanes based on the memory address. A first crossbar circuitry of the crossbar circuitries receives the first memory command from the first communication lanes, and outputs the first memory command to a first memory device of the memory devices associated with the memory.