3D Memory Interconnect Test Structures for Open-Circuit Detection
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Solution Overview
Problem
The challenge in three-dimensional (3D) non-volatile memory devices is the increasing difficulty in monitoring the yield of interconnect structures due to their high aspect ratio, leading to potential open circuits, which complicates the detection of electrical connections and reduces the accuracy of identifying faulty memory blocks.
Innovation Solution
The implementation of test structures with staircase interface portions and interconnect structures that emulate the corresponding memory sub-arrays, allowing for serial electrical coupling to detect current thresholds and identify open circuits, thereby quickly and accurately identifying problematic memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If interconnect structures with high aspect ratio are used in 3D memory devices, then vertical integration and memory density are improved, but detection of electrical connections and identification of faulty blocks becomes more difficult
Solution Approach 1:
The patent creates test structures that are copies of the actual memory blocks, including identical interconnect structures with the same high aspect ratio. These test structures allow external testing of electrical connections without requiring access to the internal memory cells, thus resolving the detection difficulty while maintaining high memory density in the actual device.
Solution Approach 2:
The patent introduces test structures as intermediary elements between the external testing equipment and the internal interconnect structures. These test structures serve as mediators that replicate the electrical characteristics of the actual interconnects, enabling indirect measurement and detection of connection integrity without direct access to the high-aspect-ratio interconnects themselves.
2Measurement precision
If test structures are added to emulate memory sub-arrays, then accuracy of identifying faulty memory blocks is improved, but device complexity increases
Solution Approach 1:
The patent segments the device into functional memory blocks and test structures. The test structures are separate, dedicated segments that replicate only the necessary interconnect characteristics for testing, allowing accurate fault identification without duplicating the entire memory array complexity.
Solution Approach 2:
The test structures are placed locally adjacent to the memory blocks they test, rather than requiring global testing infrastructure. Each test structure is locally optimized to match the specific interconnect characteristics of its corresponding memory block, improving measurement precision while minimizing overall device complexity through localized rather than universal testing capability.
Data Source
AI summary
A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.