3D Memory Interconnect Segmentation to Prevent Contact Plug Blockage
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in improving yield due to potential inclines in stacked interconnects during the formation process, which can lead to blockages and prevent the formation of contact plugs, especially in areas with asymmetrical configurations and complex interconnect structures.
Innovation Solution
The semiconductor memory device incorporates a dividing portion with alternating insulating layers between interconnect layers, allowing for the division of interconnects and preventing deformation during the formation process, thereby ensuring proper alignment and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect layers are formed in a three-dimensional memory structure for higher integration, then device capacity and integration are improved, but the interconnects may incline during formation which can lead to blockages and prevent contact plug formation
Solution Approach 1:
The interconnect structure is divided into multiple segments by inserting dividing portions between adjacent interconnects. These dividing portions include insulating layers that physically separate the interconnects, preventing them from inclining toward each other during the formation process. This segmentation maintains manufacturing precision while enabling three-dimensional memory structures for higher capacity.
2Adaptability or versatility
If the memory structure uses asymmetrical configurations and complex interconnect structures, then device functionality is improved, but yield decreases due to potential inclines and blockages during formation
Solution Approach 1:
Dividing portions consisting of insulating layers are introduced as intermediary structures between adjacent interconnects. These intermediaries prevent direct interaction between interconnects that could lead to inclining and blockages, thereby maintaining high manufacturing yield even in asymmetrical and complex memory configurations.
3Productivity
If interconnect layers are stacked closely for higher integration, then device capacity increases, but the risk of inclines and blockages during contact plug formation increases
Solution Approach 1:
By segmenting the interconnect structure with dividing portions, the patent enables closer stacking of interconnect layers for higher integration density while simultaneously preventing inclines that would complicate contact plug formation. The insulating layers in the dividing portions act as physical barriers that maintain interconnect separation throughout the manufacturing process.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes interconnect layers stacked above a substrate; a memory pillar configured to penetrate the interconnect layers; a first member and a second member; and a dividing portion provided between the first member and the second member. The dividing portion includes insulating layers. The insulating layers each include a first portion and a second portion. The first portion is provided between the first member and the second portion. The second portion is provided between the first portion and the second member. The first portion and the second portion each have an individual arc shape when viewed from a top and are in contact with each other.