Semiconductor Memory Interconnects for Stress Balancing
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Solution Overview
Problem
The existing stacked semiconductor memory devices face challenges due to stress generated in electrode layers, leading to wafer warp and patterning precision issues, as the electrode layers are prone to compressive or tensile stress, making it difficult to maintain substrate stability during manufacturing.
Innovation Solution
The semiconductor memory device incorporates interconnect portions that extend in a direction orthogonal to the electrode layers, balancing tensile stress and reducing substrate warp by providing a material with tensile stress, such as silicon nitride, to mitigate the stress differences between directions, and includes a method for efficient erasure operations by electrically connecting these interconnects to the channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrode layers are formed using metal material, then electrical conductivity is improved, but substrate warp increases due to stress
Solution Approach 1:
The patent introduces interconnect portions made of metal material that extend in the first direction to generate tensile stress, which counteracts the compressive stress in the electrode layers extending in the second direction. This stress balancing approach prevents substrate warp while maintaining electrical conductivity of the metal electrode layers.
Solution Approach 2:
The patent changes the stress parameter by introducing interconnect portions with tensile stress to compensate for the compressive stress in the electrode layers. By adjusting the stress parameters through material selection and structural design, the substrate warp is controlled while preserving the electrical properties.
2Reliability
If electrode layers are made long in one direction, then electrical connection is improved, but wafer warp becomes large due to stress
Solution Approach 1:
The patent introduces interconnect portions made of metal material that extend in the first direction to generate tensile stress, which counteracts the compressive stress in the electrode layers extending in the second direction. This stress balancing approach prevents substrate warp while maintaining electrical conductivity of the metal electrode layers.
Solution Approach 2:
The patent addresses the stress issue by introducing interconnect portions in a different orientation (first direction) perpendicular to the electrode layers (second direction). This dimensional approach allows electrical connection while balancing stress through orthogonal structural elements.
3Stability of the object's composition
If interconnect portions are added to balance stress, then substrate warp is reduced, but device complexity increases
Solution Approach 1:
The interconnect portions serve dual functions: they provide electrical connection between different layers and simultaneously balance the stress in the substrate. This multi-functionality reduces the need for separate stress-compensation structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent combines the electrical connection function and stress balancing function into a single interconnect structure. By merging these functions, the design avoids adding separate components for stress management, thus controlling device complexity while achieving substrate stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces substrate warp and improves manufacturing stability, enhances erase operation efficiency by reducing interconnect delay, and allows for a more compact memory region layout, facilitating better integration of peripheral circuits.
Implementation Method 1
When the electrode layers are formed using a metal, stress such as compressive stress, tensile stress, or the like is generated in the electrode layers
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar portions. At least one portion of the interconnect portions is provided inside the substrate, each of the interconnect portions extends in a first direction along a surface of the substrate, and the interconnect portions are arranged along a second direction crossing the first direction. The conductive layer is provided on the interconnect portions. The stacked body is provided on the conductive layer and includes electrode layers stacked to be separated from each other, and each of the electrode layers extends in the second direction. The columnar portions are provided inside the stacked body, each of the columnar portions includes a semiconductor portion extending in a stacking direction of the electrode layers and a charge storage film provided between the semiconductor portion and the stacked body.