Memory Cell Interconnect Layout With Uniform SL/BL Pitch
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Solution Overview
Problem
Existing semiconductor memory structures face challenges with uneven source line (SL) and bit line (BL) pitches, leading to asymmetric layouts that complicate manufacturing and design due to uneven capacitance and non-uniform access times.
Innovation Solution
The introduction of an intervening conductive layer and separation of even and odd metal lines into different layers allows for an even SL/BL line pitch and a symmetric layout structure, mitigating the uneven line pitch issue and achieving a symmetric interconnect layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell layout is used, then integration density can be increased, but uneven source line and bit line pitches result in asymmetric layouts that complicate manufacturing and design
Solution Approach 1:
The patent introduces an additional metal layer (third metal layer) to accommodate bit lines, separating them from the planar source line layout. This vertical dimensionality change allows source lines to be arranged with uniform pitch in the first metal layer while bit lines in the third metal layer can be positioned to achieve uniform pitch, eliminating the asymmetric layout problem without increasing planar complexity
Solution Approach 2:
The patent segments the interconnect structure into distinct metal layers: first metal layer for source lines, second metal layer for word lines, and third metal layer for bit lines. This segmentation allows each layer to be optimized independently for uniform pitch requirements, simplifying manufacturing by treating each layer as a separate routing domain with consistent spacing
2Reliability
If conventional interconnect structure is used, then device functionality is achieved, but uneven line pitch causes non-uniform access times and capacitance
Solution Approach 1:
By moving bit lines to the third metal layer above the planar source line array, the patent creates a three-dimensional interconnect architecture where bit lines can uniformly access memory cells through vertical vias. This vertical separation ensures that all bit lines have equivalent capacitance to their associated source lines and memory cells, achieving uniform access times across the array
Solution Approach 2:
The patent achieves equipotentiality in terms of electrical characteristics by ensuring uniform pitch spacing between all bit lines and their associated source lines. The consistent geometric arrangement across all metal layers creates equivalent electrical paths and capacitance values, making all memory cell accesses experience uniform electrical conditions
Data Source
AI summary
A semiconductor structure includes a first cell, a second cell, a first bit line, a first source line, a second bit line, and a second source line. The first cell includes a first source structure and a first drain structure. The second cell includes a second source structure and a second drain structure. The first bit line is coupled to the first drain structure, the first source line is coupled to the first source structure, the second bit line is coupled to the second drain structure, and the second source line is coupled to the second source structure. The first source line and the first bit line are alternately arranged, and the second source line and the second bit line are alternately arranged. A distance between the first source line and the first bit line is similar to a distance between the second source line and the second bit line.