Memory Interconnect Write Transaction Coherence via Segmentation
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Solution Overview
Problem
In data processing systems with shared memory and transaction masters, maintaining data coherence across local caches and shared memory is challenging, leading to potential inconsistencies and the need for stalling or buffering write transactions to ensure correct ordering, which increases storage requirements and delays.
Innovation Solution
The implementation of write control circuitry and serialisation circuitry that allows write transactions to proceed in what would be considered an incorrect order by storing portion data identifying written portions and preventing overwrites, while serialisation circuitry stalls transactions until cache invalidation and write transactions are completed, avoiding the need for buffering and stalling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write transactions are stalled or buffered to ensure correct ordering, then data coherence is maintained, but storage requirements increase and transaction delays occur
Solution Approach 1:
The write transaction is segmented into two independent operations: (1) sending the write transaction to shared memory without waiting for cache invalidation, and (2) separately invalidating the cache line. This segmentation allows the write to proceed without buffering while maintaining coherence through the separate invalidation operation.
Solution Approach 2:
The cache invalidation is performed as a preliminary action before the write transaction is sent to shared memory. By invalidating the cache line first, the system ensures that no stale data can overwrite the new write data, eliminating the need for buffering while maintaining coherence.
2Reliability
If write transactions are stalled or buffered to ensure correct ordering, then data coherence is maintained, but transaction processing time increases
Solution Approach 1:
The write transaction is segmented into two independent operations: (1) sending the write transaction to shared memory without waiting for cache invalidation, and (2) separately invalidating the cache line. This segmentation allows the write to proceed without buffering while maintaining coherence through the separate invalidation operation.
Solution Approach 2:
The cache invalidation is performed as a preliminary action before the write transaction is sent to shared memory. By invalidating the cache line first, the system ensures that no stale data can overwrite the new write data, eliminating the need for buffering while maintaining coherence.
3Productivity
If local cache memories are provided to increase access speed, then transaction efficiency improves, but data coherence management complexity increases
Solution Approach 1:
The coherence management function is extracted from the write transaction path and implemented as a separate, independent operation. Instead of buffering writes to maintain coherence, the system extracts the invalidation operation and performs it separately, simplifying the write path while maintaining coherence.
Solution Approach 2:
The system uses feedback from the cache invalidation operation to ensure coherence. After invalidating the cache line, the system waits for the invalidation to complete before allowing subsequent reads, ensuring that all transactions see consistent data without complex buffering mechanisms.
Data Source
AI summary
A memory interconnect between transaction masters and a shared memory. A first snoop request is sent to other transaction masters to trigger them to invalidate any local copy of that data they may hold and for them to return any cached line of data corresponding to the write line of data that is dirty. A first write transaction is sent to the shared memory. When and if any cached line of data is received from the further transaction masters, then the portion data is used to form a second write transaction which is sent to the shared memory and writes the remaining portions of the cached line of data which were not written by the first write transaction in to the shared memory. The serialization circuitry stalls any transaction requests to the write line of data until the first write transaction.