Memory Interface Address Bus Segmentation for Interconnection Reduction
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Solution Overview
Problem
As memory cell density increases, the number of external interconnections required for input and output signals also increases, leading to a conflict with the design motivations of miniaturization and integration in memory devices, particularly in synchronous random access memories (SDRAMs).
Innovation Solution
The proposed solution involves a two-phase activation process for memory access, where the upper and lower portions of the address signals are provided in separate phases, with some phases embedded within existing commands like PRECHARGE or REFRESH, reducing the number of external interconnections needed without introducing significant latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of memory cells increases to achieve higher density, then the storage capacity is improved, but the number of external interconnections required increases
Solution Approach 1:
The address bus is segmented into two separate buses: an upper address bus for transmitting upper address bits and a lower address bus for transmitting lower address bits. This segmentation allows the memory device to be addressed with fewer external interconnections at any given time, as the address space is divided and transmitted in phases rather than requiring all address lines simultaneously.
Solution Approach 2:
The patent introduces a time dimension to the address transmission process by implementing a two-phase activation sequence. The upper and lower address bits are transmitted at different times through separate buses, transforming the spatial problem of reducing interconnection count into a temporal sequence of operations. This allows the memory device to maintain high density without proportionally increasing the number of physical interconnections.
2Length of moving object
If the number of external interconnections is reduced for miniaturization, then the device size is improved, but the ability to address all memory cells is compromised
Solution Approach 1:
The addressing capability is segmented across two separate activation phases. The upper address bus handles upper address bits during the first phase, and the lower address bus handles lower address bits during the second phase. This segmentation preserves the full addressing capability despite having fewer interconnections available at any single moment, as the complete address is assembled through the sequential operation of both buses.
Solution Approach 2:
The upper address bits are transmitted and latched in advance during the first activation phase before the lower address bits are transmitted in the second phase. This preliminary action allows the memory device to prepare part of the address information early, maintaining full addressing capability while using fewer simultaneous interconnections. The preliminary transmission of upper address bits enables the device to efficiently combine this information with the subsequently transmitted lower address bits.
Data Source
AI summary
Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.