Memory Interface Address Match Table for Spare Cell Replacement
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Solution Overview
Problem
As memory cells in low latency devices like DRAM shrink due to advancements in process technology, they become more susceptible to errors from aging and repeated accesses, leading to increased weak bits that conventional methods struggle to correct, resulting in reduced data retention time and memory performance.
Innovation Solution
Implementing a memory interface device with an address match table and control module that dynamically replaces faulty memory cells with spare cells, using an enhanced memory interface circuit to reroute addresses and commands, thereby maintaining memory performance by utilizing externally addressable spare columns to provide reliable storage locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are shrunk due to process technology advancements, then memory capacity increases, but data retention time decreases and weak bits increase
Solution Approach 1:
The patent pre-identifies weak memory cells during manufacturing or initial operation and maps them to spare cells before they become faulty. The address match table is pre-populated with mappings from weak cell addresses to spare cell addresses, enabling proactive replacement rather than reactive repair when errors occur.
Solution Approach 2:
The patent introduces an address match table as an intermediary component between the memory controller and the physical memory cells. This table acts as a translation layer that intercepts access requests to weak cells and redirects them to corresponding spare cells, transparently handling the replacement without requiring changes to the memory interface or controller logic.
2Reliability
If conventional error correction methods are used, then some weak bits can be corrected, but they struggle to correct increased weak bits from shrinking cells
Solution Approach 1:
The patent implements a dynamic replacement strategy where the address match table can be updated to reflect newly identified weak cells. As cells degrade over time due to aging or repeated accesses, the system can dynamically add new mappings to the address match table, allowing continuous adaptation to changing memory cell reliability characteristics.
Solution Approach 2:
The patent segments the memory address space into two categories: healthy cells and weak cells requiring replacement. The address match table maintains separate mappings for these segments, allowing the system to selectively redirect only problematic addresses while leaving healthy cell accesses unchanged, thereby minimizing overhead and maintaining high performance.
3Reliability
If spare cells are used to replace faulty cells, then memory reliability improves, but device complexity increases due to address mapping requirements
Solution Approach 1:
The address match table is designed to be self-populated through a testing and characterization process that automatically identifies weak cells and generates the appropriate mappings. Once established, the table operates autonomously, requiring no manual intervention or complex control logic to function. The system essentially services itself by automatically detecting and redirecting accesses to weak cells.
Solution Approach 2:
The address match table serves multiple functions: it acts as a lookup table for weak cell replacement, a characterization record of memory cell reliability, and a dynamic configuration structure that can be updated over time. This multi-functionality reduces the need for separate components or mechanisms, thereby limiting the increase in device complexity.
Data Source
AI summary
A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.