Memory Interface Address Match Table for Faulty Cell Replacement
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Solution Overview
Problem
As memory cells in low latency devices like DRAM shrink due to advancements in process technology, they become more susceptible to errors from aging and repeated accesses, leading to increased weak bits that conventional methods fail to adequately address, as they assume infinite endurance and do not account for degradation.
Innovation Solution
Implementing a memory interface device with an Address Match Table and a control module that dynamically replaces faulty memory cells with spare cells, using an enhanced memory interface circuit to reroute addresses and commands, thereby maintaining data integrity and presenting a contiguous memory address space without faulty locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are shrunk to increase memory capacity, then storage density is improved, but data retention time deteriorates due to increased leakage and reduced storage capacitance
Solution Approach 1:
The patent applies preliminary action by performing weak cell identification and mapping during the manufacturing process before the memory device is deployed. The address match table is pre-populated with weak cell addresses and their corresponding spare cell mappings, so that when the memory device operates, any access to weak cells is automatically redirected to healthy spare cells without requiring runtime detection or intervention. This preliminary preparation ensures data integrity while maintaining the benefits of scaled-down cell sizes.
2Ease of manufacture
If conventional memory mapping methods are used, then manufacturing simplicity is maintained, but reliability deteriorates due to inability to handle degradation from aging and repeated accesses
Solution Approach 1:
The patent applies dynamics by implementing a multi-level mapping system that can adapt to different failure modes. The address match table dynamically handles various scenarios including weak cells, bad blocks, and degraded regions by redirecting accesses to appropriate spare areas. This dynamic redirection capability allows the system to maintain high reliability throughout the device lifetime, accommodating aging effects and wear from repeated accesses while preserving manufacturing simplicity through a unified mapping approach.
Data Source
AI summary
A memory interface device has an address input(s) configured to receive address information from an address stream of a host controller; an address output(s) configured to drive address information, and is coupled to a plurality of memory devices; an address match table comprising at least a revised address corresponding to a spare memory location; a control module configured to determine address information from an address stream from an address command bus coupled to a host controller during a run time operation; and a multiplexer coupled to the address input and coupled to the address output.