Memory Interface Circuit Balancing Serial Data Links
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Solution Overview
Problem
High-speed networking applications face memory bottlenecks due to limited I/O pins in programmable ICs, leading to insufficient off-chip bandwidth and inefficient memory access, which is exacerbated by the need for parallel interfaces and separate memory controllers.
Innovation Solution
A circuit and method that utilize high-speed serial data links to communicate with external memory by sorting and balancing read and write transactions based on data sizes, optimizing the order of transactions to maximize bandwidth utilization across unidirectional serial data links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If parallel memory interfaces are implemented to increase bandwidth, then off-chip bandwidth is improved, but the number of I/O pins required increases beyond available package pins
Solution Approach 1:
The patent replaces parallel mechanical I/O connections with serial communication. Instead of using multiple parallel data buses requiring numerous physical pins, the invention uses serial data links to transmit memory transactions, significantly reducing the number of I/O pins while maintaining or increasing effective bandwidth through time-multiplexed serial communication
Solution Approach 2:
The patent transitions from spatial parallelism (multiple simultaneous data paths) to temporal parallelism (time-multiplexed serial paths). By ordering transactions strategically across time on serial links, the system achieves high bandwidth utilization without requiring multiple physical channels, effectively adding a time dimension to compensate for reduced spatial dimension
2Ease of operation
If memory transactions are processed in received order, then transaction simplicity is maintained, but data link utilization becomes unbalanced and inefficient
Solution Approach 1:
The patent applies preliminary ordering of transactions before transmission. The memory interface circuit analyzes incoming read and write transactions, determines their sizes, and pre-orders them in a sequence that will balance data link utilization. This preliminary arrangement ensures efficient use of serial data links without adding complexity during actual transmission, as the ordering logic is resolved in advance
Solution Approach 2:
The patent incorporates feedback mechanisms where the memory interface circuit monitors transaction sizes and adjusts the ordering of subsequent transactions based on observed data link utilization patterns. This feedback-driven dynamic ordering optimizes bandwidth utilization by adapting to varying transaction characteristics while maintaining operational simplicity through automated control
Data Source
AI summary
In one embodiment, a circuit for communicating with a memory is provided. The circuit includes a sorting circuit configured to receive a plurality of read and write transactions. The sorting circuit sorts the write transactions according to respective sizes of data to be written to the memory, and sorts the read transactions according to respective sizes of data to be read from the memory. A selection circuit is configured to select transactions for transmission to the memory, from the sorted read and write transactions, in an order that balances a quantity of data to be written to the memory over a first serial data link with a quantity of data to be read from the memory over a second serial data link. A transmitter is coupled to the selection circuit and is configured to transmit the selected transactions to the memory device on a serial data link.