Memory Interface BER Estimation for Faster LDPC Decoding
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Solution Overview
Problem
Current data storage devices face increased latency due to high bit error rates (BER) when using low-density parity-check (LDPC) error correction coding, as they often require additional operations to determine soft bits and process subcodes sequentially, regardless of individual BER levels.
Innovation Solution
Relocating BER estimation to the memory interface within the controller, allowing on-the-fly BER calculation based on hard bits, and using these estimates to selectively request soft bits and reorder subcode decoding, thereby optimizing decoding modes and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft bits are used to improve error correction capability when BER is high, then error correction capability is improved, but additional sense and data transfer operations increase overall latency
Solution Approach 1:
The patent changes the parameter of BER estimation timing from after decoding to before decoding (at the memory interface). This allows the system to determine in advance whether soft bits are needed, enabling conditional retrieval only when necessary. The BER estimate threshold serves as a parameter change that triggers different decoding paths, optimizing the balance between error correction capability and latency by avoiding unnecessary soft bit operations when BER is low.
2Reliability
If soft bits are provided for an entire page of data when average BER is high, then error correction capability is improved, but unnecessary operations increase latency for sub codes with low BER
Solution Approach 1:
The patent segments the page-level BER assessment into individual sub-code level BER estimates. Instead of treating the entire page as a single unit, the system calculates BER estimates for each sub-code separately at the memory interface. This segmentation enables selective application of soft bits only to specific sub-codes that require them, rather than applying soft bit operations uniformly across the entire page, thereby reducing unnecessary operations and latency.
Solution Approach 2:
The patent applies partial action by providing soft bits only to the extent necessary - specifically to sub-codes whose BER estimates exceed the threshold. Rather than providing soft bits for the entire page when average BER is high, the system provides soft bits selectively to individual sub-codes that need them, avoiding excessive operations on sub-codes with low BER and reducing overall latency.
3Ease of operation
If sub codes are processed in the same order regardless of individual BER, then processing simplicity is maintained, but latency increases due to inability to optimize decoding sequence
Solution Approach 1:
The patent introduces dynamics into the sub-code processing sequence by reordering sub-codes based on their individual BER estimates. Instead of a fixed processing order, the system dynamically adjusts the sequence to process sub-codes with lower BER first and those with higher BER later. This dynamic reordering optimizes latency by enabling early termination for easily decodable sub-codes while ensuring that sub-codes requiring soft bits are processed when resources are available.
Data Source
AI summary
A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.