Semiconductor Memory Device Interface Layer Boron Barrier

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The complexity of manufacturing processes for semiconductor memory devices increases due to varying structural designs of MOS transistors, leading to complications in integrating memory cell and non-memory cell device processes, and issues with boron penetration and material layer reactions causing defects.

Innovation Solution

A patterned conductive structure is formed with a silicon conductive layer, an oxygen-containing interface layer, a barrier layer, and a metal conductive layer, where the interface layer blocks boron penetration and prevents serious reactions between silicon and other material layers, enhancing manufacturing yield and electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a patterned conductive structure with multiple layers is formed to improve electrical performance, then conductivity and device performance are improved, but boron penetration and material layer reactions cause defects

Engineering Contradiction:
Improveelectrical performanceVSAvoidboron penetration and material reactions
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An interface layer is inserted between the first silicon conductive layer and the second silicon conductive layer to act as a mediator. This interface layer prevents boron penetration from the second silicon conductive layer into the first silicon conductive layer, and also prevents serious reactions between the silicon conductive layers and other material layers, thereby eliminating defects while maintaining electrical performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If MOS transistors have different structural designs to meet product specifications and memory cell density requirements, then device functionality and density are improved, but manufacturing process complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The interface layer serves multiple functions simultaneously: it blocks boron penetration, prevents serious reactions between silicon conductive layers and other material layers, and maintains electrical performance. This multi-functional approach allows different MOS transistor structural designs to be integrated without significantly increasing manufacturing process complexity, as the same interface layer structure can be applied across different device regions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The interface layer effectively blocks boron penetration and material layer reactions, improving the electrical performance and manufacturing yield of semiconductor memory devices by preventing defects and ensuring better integration of memory cell and non-memory cell processes.

Implementation Method 1

The interface layer may be used to block boron penetration effects

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

prevent the silicon conductive layer from reacting with other material layers too seriously and forming defects

Methodology Applied
Scientific EffectChemical barrier:

Data Source

PatentUS20190221571A1Semiconductor memory device and manufacturing method thereof
Publication Date: 2019.07.18 UNITED MICROELECTRONICS CORP
  • US20190221571A1 patent drawing
  • US20190221571A1 patent drawing
  • US20190221571A1 patent drawing

AI summary

A semiconductor memory device includes a semiconductor substrate and a patterned conductive structure. The patterned conductive structure is disposed on the semiconductor substrate. The patterned conductive structure includes a first silicon conductive layer, a second silicon conductive layer, an interface layer, a barrier layer, and a metal conductive layer. The second silicon conductive layer is disposed on the first silicon conductive layer. The interface layer is disposed between the first silicon conductive layer and the second silicon conductive layer, and the interface layer includes oxygen. The barrier layer is disposed on the second silicon conductive layer. The metal conductive layer is disposed on the barrier layer.