Memory Interface Buffer Chip Bridging Parallel and Serial Buses
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Solution Overview
Problem
Current memory controllers lack the Advanced Memory Buffer (AMB) interface, limiting their ability to connect with Fully Buffered Dual In-line Memory Modules (FB-DIMMs, and thus restrict the performance of memory systems, especially as the number of memory modules increases.
Innovation Solution
A memory interface buffer chip is introduced to connect a conventional memory controller to FB-DIMMs, using a printed circuit board with a memory interface buffer chip that bridges the parallel and serial memory buses, enabling the use of conventional memory controllers with FB-DIMMs through a buffer on board, and incorporating a pseudo differential digital logic circuit and adaptive power-supply regulator to enhance data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional memory controllers are used without AMB interface, then device complexity is reduced, but adaptability to FB-DIMM technology is lost
Solution Approach 1:
The patent introduces an intermediary device (memory interface adapter or AMB interface card) that bridges the conventional parallel memory controller and the serial FB-DIMM modules. This intermediary contains the AMB interface logic and protocol conversion capabilities, allowing legacy controllers to work with new FB-DIMM technology without modifying the controller itself.
Solution Approach 2:
The memory interface functionality is segmented into separate components: the conventional memory controller remains unchanged, while the AMB interface capabilities are isolated in a separate adapter or card. This segmentation allows independent upgrading of the interface layer without affecting the core controller architecture.
2Productivity
If stub bus architecture is used to connect memory modules, then device complexity is reduced, but channel performance decreases as number of modules increases
Solution Approach 1:
The patent replaces the traditional parallel stub bus architecture with a serial point-to-point connection system. This substitution transitions from a shared mechanical/electrical bus structure to individual dedicated serial links, eliminating the performance degradation caused by increasing module counts on a shared bus.
Solution Approach 2:
The memory interface architecture is made dynamic by allowing flexible configuration of serial links between the memory controller, AMB interface, and multiple FB-DIMM modules. The system can adaptively manage data flow across multiple independent serial channels, optimizing performance based on the number and configuration of memory modules.
3Speed
If parallel memory bus is used between memory controller and FB-DIMM, then data transmission speed is maintained, but power consumption and noise increase
Solution Approach 1:
The patent changes the fundamental transmission parameters from parallel voltage-based signaling to serial differential signaling. This parameter change enables high-speed data transmission while reducing power consumption and electromagnetic noise, as serial differential pairs are more energy-efficient and produce less interference compared to wide parallel buses.
Data Source
AI summary
A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect a memory controller of core logic and an advanced memory buffer (AMB). The memory controller has a memory interface for a parallel memory bus.