Memory Interface Circuit With Fixed- and Variable-Length Burst Modes
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Solution Overview
Problem
Existing memory access technologies suffer from high latency due to the long round trip latency of the CPU to transmit instructions to memory and return data, particularly in data-intensive applications like AI and big data, which involve significant memory access transactions.
Innovation Solution
A memory interface circuit is introduced that enables switching between fixed length and variable length burst transmission modes, reducing the need for address and command bits during data transfers, thereby increasing memory bus bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the CPU transmits instructions to memory and returns data using traditional memory access methods, then data can be fetched from physical memory, but the round trip latency is long and data access is time-consuming
Solution Approach 1:
The patent implements a cache memory system that pre-loads and stores frequently accessed data blocks before they are needed by the CPU. The cache controller predicts which data will be needed and loads it into the cache memory in advance, eliminating the need to wait for slow main memory access during actual data retrieval operations.
Solution Approach 2:
The patent introduces cache memory as an intermediary layer between the CPU and main memory. This intermediate storage layer provides fast access to frequently used data, reducing the direct interaction frequency between the CPU and slow main memory, thereby decreasing overall access latency while maintaining high data transfer speeds.
2Quantity of substance
If address and command bits are transmitted for every memory access, then precise memory locations can be accessed, but the memory bus bandwidth is reduced due to the overhead of control bits
Solution Approach 1:
The patent segments memory access operations into cache-level transactions and main memory transactions. At the cache level, simplified addressing is used for fast access to previously loaded data blocks. Only when cache misses occur does the system engage in full main memory access with complete address and command bit transmission, thereby reducing overall control overhead and increasing effective bandwidth.
Solution Approach 2:
The patent implements partial address transmission by using tag-based addressing in the cache system. Instead of transmitting full memory addresses for every access, the system transmits only partial address information (tags) that can identify cached data blocks, reducing the number of control bits required while maintaining precise memory access capability.
Data Source
AI summary
A memory interface circuit includes a request decoder configured to receive a command signal and an address signal. The request decoder is configured to decode the command signal and the address signal to generate a data count signal and a start address signal. A burst counter is coupled to the request decoder, and the burst counter is configured to update the data count signal after each access of a memory. An address generator is coupled to the request decoder. The address generator is configured to receive the start address signal and generate a subsequent memory address signal based on the start address signal after each access of the memory.