Memory Interface Burst Switching for Higher Bus Bandwidth
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Solution Overview
Problem
Existing memory access technologies suffer from high latency due to the long round trip latency of CPU instructions to and from memory, particularly in data-intensive applications like AI and big data, where significant memory access transactions are required, and data movement degrades memory bus bandwidth.
Innovation Solution
Implementing a memory interface circuit that allows switching between fixed length and variable length burst transmission modes, reducing the need for address and command bits during data transfers, especially in burst mode, thereby increasing memory bus bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional fixed-length transmission mode is used for memory access, then address and command information can be accurately transmitted, but memory bus bandwidth is reduced due to the overhead of address and command bits during data transfers
Solution Approach 1:
The memory interface circuit dynamically switches between fixed-length transmission mode and variable-length burst transmission mode based on the operation type. For data migration operations, it selects variable-length burst mode to maximize bandwidth by eliminating address and command overhead. For normal memory access, it uses fixed-length mode to ensure accurate address and command transmission. This dynamic adaptation resolves the contradiction between information accuracy and bandwidth efficiency.
Solution Approach 2:
The system changes the transmission mode parameter from fixed-length to variable-length burst mode depending on the operation requirements. By modifying this parameter, the system can eliminate address and command bits during bulk data transfers, thereby increasing memory bus bandwidth while maintaining information accuracy when needed through mode switching.
2Productivity
If variable length burst transmission mode is used to increase bandwidth, then memory bus bandwidth is improved, but the system becomes more complex due to mode switching requirements
Solution Approach 1:
The memory interface circuit includes an operation type detection unit that automatically detects whether the current operation is a data migration or normal memory access, and autonomously selects the appropriate transmission mode. This self-service mechanism reduces the need for external control logic and simplifies the overall system complexity while maintaining high bandwidth efficiency.
Solution Approach 2:
The memory interface circuit is designed to handle multiple operation types (normal memory access and data migration) using a single unified structure that can switch between fixed-length and variable-length transmission modes. This multi-functionality eliminates the need for separate dedicated circuits for different operations, thereby reducing device complexity while achieving high bandwidth.
3Measurement precision
If address and command bits are transmitted for every memory access, then precise memory location identification is ensured, but data transmission efficiency is reduced due to the overhead of these control bits
Solution Approach 1:
The transmission protocol is segmented into two distinct modes: fixed-length mode for precise address and command transmission, and variable-length burst mode for efficient data transfer. By segmenting the transmission approach based on operation type, the system achieves both precise memory location identification when needed and high data transmission efficiency during bulk operations.
Solution Approach 2:
Instead of transmitting address and command bits for every single memory access, the system applies partial action by transmitting these control bits only when necessary (for normal memory access operations). For data migration operations, it uses excessive action in the form of variable-length burst transmission that transfers data without repeated address and command overhead, thereby optimizing overall transmission efficiency.
Data Source
AI summary
A memory interface circuit includes a request decoder configured to receive a command signal and an address signal. The request decoder is configured to decode the command signal and the address signal to generate a data count signal and a start address signal. A burst counter is coupled to the request decoder, and the burst counter is configured to update the data count signal after each access of a memory. An address generator is coupled to the request decoder. The address generator is configured to receive the start address signal and generate a subsequent memory address signal based on the start address signal after each access of the memory.