Memory System Interface Circuit for Cross-Protocol Conversion
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Solution Overview
Problem
Existing memory systems face inefficiencies in data transfer due to different interface protocols between memory controllers and non-volatile memories, leading to decreased data transmission efficiency and difficulty in direct communication.
Innovation Solution
A memory system with an interface circuit that performs channel conversion, allowing compatibility between controllers and non-volatile memories supporting different interface protocols by converting data channels to control channels or vice versa, using serializers, decoders, and retimers to correct timing and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the non-volatile memory and controller use different interface protocols, then compatibility between old and new devices is improved, but data transfer efficiency deteriorates due to protocol conversion requirements
Solution Approach 1:
The patent introduces an interface circuit as an intermediary component between the controller and non-volatile memory devices. This interface circuit supports multiple interface protocols (first and second protocols) and automatically selects the appropriate protocol for communication, enabling compatibility between devices using different protocols without sacrificing data transfer efficiency.
2Device complexity
If data is transferred through the same input/output pins used for commands and addresses, then pin usage is optimized, but data transfer efficiency deteriorates because data cannot be transferred simultaneously with commands or addresses
Solution Approach 1:
The patent implements dynamic pin function assignment where the input/output pins can switch between different functions (data transfer, command reception, address reception) based on the current operation phase. This dynamic switching enables the pins to be reused efficiently while maintaining high data transfer rates through parallel operation of different signal types.
Solution Approach 2:
The interface circuit employs periodic action by dividing the communication process into distinct time periods or phases, where different pins are assigned to different functions in alternating cycles. This allows data, commands, and addresses to be transferred in an interleaved manner, improving overall system throughput while maintaining pin efficiency.
Data Source
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AI summary
A memory system (10) includes a plurality of memory devices (NVM11-NVM14, NVM21-NVM24), each connected to one of a plurality of internal channels (CHI1, CHI2) respectively including an internal data channel and an internal control channel, and each configured to perform communication based on a first interface protocol, a controller (110) connected to an external channel (CHO) including an external data channel and an external control channel and configured to perform communication based on a second interface protocol, and an interface circuit (130) connecting the external channel (CHO) to each of the internal channels (CHI1, CHI2). The interface circuit (130) is configured to perform channel conversion by serializing a parallel data signal received from the controller (110) through the external data channel and outputting the serialized signal to the internal control channel included in a first one of the internal channels, or parallelizing a signal received through the external control channel and outputting the parallelized signal to the internal data channel included in the first one of the internal channels.