Semiconductor Memory Interface Circuit Synchronization
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Solution Overview
Problem
Semiconductor integrated circuits face challenges in synchronizing read data from external DDR-SDRAM with internal clocks accurately and stably, particularly due to variations in I/O buffer delay caused by process, temperature, and power supply voltage fluctuations, leading to potential malfunctions and signal reflection issues.
Innovation Solution
A microcomputer with a memory interface circuit and clock generator that measures the delay of the data strobe signal relative to the internal clock, generates a phase-shifted signal, and synchronizes read data using this information, allowing for accurate timing compensation without signal reflection, and includes a variable delay circuit for precise phase shift adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock output from the memory controller is fed back to the SDRAM to phase-match the clock signal with an internal clock signal, then synchronization accuracy is improved, but signal reflection occurs causing malfunctions
Solution Approach 1:
The patent introduces a delay element as an intermediary component between the memory controller output and the SDRAM clock input. This delay element adjusts the timing of the clock signal to match the internal clock phase without requiring direct feedback connection, thereby achieving synchronization while avoiding signal reflection issues that would occur with direct feedback wiring.
2Adaptability or versatility
If the I/O buffer delay is allowed to vary under process/temperature/power supply conditions, then device adaptability is improved, but timing stability deteriorates with variations up to 2 cycles of reference clock
Solution Approach 1:
The patent employs a feedback mechanism where the delay element's timing is dynamically adjusted based on detection of the actual delay amount. The system measures the delay under various process, temperature, and power supply conditions, then adjusts the delay element accordingly to maintain stable timing synchronization, effectively compensating for environmental variations.
Solution Approach 2:
The delay element is designed with variable delay capability that can be dynamically adjusted based on operating conditions. This dynamic adjustment allows the system to adapt to changing process, temperature, and power supply conditions while maintaining stable timing, transforming a static component into a responsive, condition-dependent timing control element.
3Productivity
If clock frequency for interface with external synchronous memory is increased, then productivity is improved, but timing control difficulty increases making synchronization inaccurate
Solution Approach 1:
The delay element serves as a timing intermediary that can be precisely controlled to compensate for high-frequency timing variations. By inserting this adjustable delay component in the clock path, the system achieves accurate timing control at high clock frequencies without requiring complex distributed timing control circuits across the entire system.
Data Source
AI summary
A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.