Memory Interface Circuit With Internal Clock Cutoff for Reliable Access
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Solution Overview
Problem
As ICs and their memories become more complex and reduced in size, there are challenges regarding the reliability of read and write operations, which are complex processes requiring precise timing sequences and waveforms, and generating multiple signals independently is difficult and often requires complex circuitry.
Innovation Solution
Generating several signals for access operations in a memory circuit from a common control signal, reducing the need for external input/output pins and incorporating an over-time protection scheme to prevent mis-program or mis-read, with adjustable time thresholds and cell counts, thereby improving power-performance-area (PPA) and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple signals are generated independently for memory access operations, then the memory circuit can perform read and write operations, but the circuit complexity increases and requires more external input/output pins
Solution Approach 1:
The patent combines multiple signal generation functions into a single integrated circuit block. The interface circuit generates clock signals, control signals, and data signals internally from a single enable signal input, eliminating the need for multiple independent external signal inputs and reducing overall circuit complexity while maintaining operational reliability
Solution Approach 2:
The interface circuit is designed as a multi-functional unit that can generate various types of signals (clock, control, data) required for different memory access operations (read, write, program, erase) from a single enable signal input, making the circuit universal for multiple memory operations without requiring separate signal generation paths
2Adaptability or versatility
If multiple external input/output pins are used for signal input, then the memory circuit can receive control signals, but the device area increases and power consumption rises
Solution Approach 1:
The interface circuit accepts a single enable signal input that serves multiple purposes: it triggers clock signal generation, control signal generation, and data input latching. This universal input approach eliminates the need for multiple dedicated input pins, reducing device area while maintaining full adaptability for various memory access operations
Solution Approach 2:
The circuit internally generates all necessary signals (clock, control, data) from the single enable signal input without requiring external provision of these signals. The interface circuit serves itself by creating its own operating signals, eliminating the need for multiple external input pins and reducing both device area and power consumption
3Productivity
If access operations are performed without time threshold control, then the memory circuit operates quickly, but mis-program or mis-read errors may occur
Solution Approach 1:
The circuit performs preliminary validation by comparing the actual pulse width against a predetermined time threshold before executing the memory access operation. This preliminary check ensures that the enable signal maintains the correct duration for reliable operation, preventing mis-program or mis-read errors while maintaining quick execution through efficient threshold comparison logic
Solution Approach 2:
The circuit incorporates feedback through the time threshold comparison mechanism that monitors the enable signal duration and controls signal generation accordingly. The feedback loop ensures that clock and control signals are only generated when the enable signal meets the minimum time requirement, providing automatic error prevention while maintaining fast operation through streamlined feedback logic
Data Source
AI summary
A memory circuit includes a memory array, and a peripheral circuit. The peripheral circuit includes an internal clock generating circuit configured to, in response to a control signal pulse, generate a series of internal clock pulses at an internal clock period corresponding to a pulse width of the control signal pulse. The peripheral circuit is configured to control an access operation in the memory array, based on the series of internal clock pulses. The internal clock generating circuit further includes a cell count circuit configured to count a current number of internal clock pulses being output in the series of internal clock pulses and, in response to the counted current number equal to an adjustable threshold corresponding to a number of memory cells, of the memory array, being accessible in the access operation, output an intermediate signal to stop outputting the series of internal clock pulses.